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570 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
570 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1792 | jermar | 29 | /** @addtogroup sparc64mm |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
570 | jermar | 35 | #include <arch/mm/tlb.h> |
36 | #include <mm/tlb.h> |
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1851 | jermar | 37 | #include <mm/as.h> |
38 | #include <mm/asid.h> |
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619 | jermar | 39 | #include <arch/mm/frame.h> |
40 | #include <arch/mm/page.h> |
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41 | #include <arch/mm/mmu.h> |
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1851 | jermar | 42 | #include <arch/interrupt.h> |
1870 | jermar | 43 | #include <interrupt.h> |
1851 | jermar | 44 | #include <arch.h> |
570 | jermar | 45 | #include <print.h> |
617 | jermar | 46 | #include <arch/types.h> |
619 | jermar | 47 | #include <config.h> |
630 | jermar | 48 | #include <arch/trap/trap.h> |
1880 | jermar | 49 | #include <arch/trap/exception.h> |
863 | jermar | 50 | #include <panic.h> |
873 | jermar | 51 | #include <arch/asm.h> |
894 | jermar | 52 | |
1891 | jermar | 53 | #ifdef CONFIG_TSB |
54 | #include <arch/mm/tsb.h> |
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55 | #endif |
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56 | |||
2141 | jermar | 57 | static void dtlb_pte_copy(pte_t *t, index_t index, bool ro); |
58 | static void itlb_pte_copy(pte_t *t, index_t index); |
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59 | static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
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60 | const char *str); |
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2048 | jermar | 61 | static void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
2141 | jermar | 62 | tlb_tag_access_reg_t tag, const char *str); |
2048 | jermar | 63 | static void do_fast_data_access_protection_fault(istate_t *istate, |
2141 | jermar | 64 | tlb_tag_access_reg_t tag, const char *str); |
1851 | jermar | 65 | |
873 | jermar | 66 | char *context_encoding[] = { |
67 | "Primary", |
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68 | "Secondary", |
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69 | "Nucleus", |
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70 | "Reserved" |
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71 | }; |
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72 | |||
570 | jermar | 73 | void tlb_arch_init(void) |
74 | { |
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1793 | jermar | 75 | /* |
1905 | jermar | 76 | * Invalidate all non-locked DTLB and ITLB entries. |
1793 | jermar | 77 | */ |
1905 | jermar | 78 | tlb_invalidate_all(); |
1946 | jermar | 79 | |
80 | /* |
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81 | * Clear both SFSRs. |
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82 | */ |
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83 | dtlb_sfsr_write(0); |
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84 | itlb_sfsr_write(0); |
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897 | jermar | 85 | } |
873 | jermar | 86 | |
897 | jermar | 87 | /** Insert privileged mapping into DMMU TLB. |
88 | * |
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89 | * @param page Virtual page address. |
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90 | * @param frame Physical frame address. |
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91 | * @param pagesize Page size. |
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92 | * @param locked True for permanent mappings, false otherwise. |
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93 | * @param cacheable True if the mapping is cacheable, false otherwise. |
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94 | */ |
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2141 | jermar | 95 | void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, |
96 | bool locked, bool cacheable) |
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897 | jermar | 97 | { |
98 | tlb_tag_access_reg_t tag; |
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99 | tlb_data_t data; |
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100 | page_address_t pg; |
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101 | frame_address_t fr; |
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873 | jermar | 102 | |
897 | jermar | 103 | pg.address = page; |
104 | fr.address = frame; |
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873 | jermar | 105 | |
894 | jermar | 106 | tag.value = ASID_KERNEL; |
107 | tag.vpn = pg.vpn; |
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108 | |||
109 | dtlb_tag_access_write(tag.value); |
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110 | |||
111 | data.value = 0; |
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112 | data.v = true; |
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897 | jermar | 113 | data.size = pagesize; |
894 | jermar | 114 | data.pfn = fr.pfn; |
897 | jermar | 115 | data.l = locked; |
116 | data.cp = cacheable; |
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2009 | jermar | 117 | #ifdef CONFIG_VIRT_IDX_DCACHE |
897 | jermar | 118 | data.cv = cacheable; |
2009 | jermar | 119 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
894 | jermar | 120 | data.p = true; |
121 | data.w = true; |
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1868 | jermar | 122 | data.g = false; |
894 | jermar | 123 | |
124 | dtlb_data_in_write(data.value); |
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570 | jermar | 125 | } |
126 | |||
1852 | jermar | 127 | /** Copy PTE to TLB. |
128 | * |
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2141 | jermar | 129 | * @param t Page Table Entry to be copied. |
130 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
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131 | * @param ro If true, the entry will be created read-only, regardless of its |
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132 | * w field. |
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1852 | jermar | 133 | */ |
2141 | jermar | 134 | void dtlb_pte_copy(pte_t *t, index_t index, bool ro) |
1851 | jermar | 135 | { |
1852 | jermar | 136 | tlb_tag_access_reg_t tag; |
137 | tlb_data_t data; |
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138 | page_address_t pg; |
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139 | frame_address_t fr; |
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140 | |||
2141 | jermar | 141 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
142 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
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1852 | jermar | 143 | |
144 | tag.value = 0; |
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145 | tag.context = t->as->asid; |
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146 | tag.vpn = pg.vpn; |
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2141 | jermar | 147 | |
1852 | jermar | 148 | dtlb_tag_access_write(tag.value); |
2141 | jermar | 149 | |
1852 | jermar | 150 | data.value = 0; |
151 | data.v = true; |
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152 | data.size = PAGESIZE_8K; |
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153 | data.pfn = fr.pfn; |
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154 | data.l = false; |
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155 | data.cp = t->c; |
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2009 | jermar | 156 | #ifdef CONFIG_VIRT_IDX_DCACHE |
1852 | jermar | 157 | data.cv = t->c; |
2009 | jermar | 158 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
1864 | jermar | 159 | data.p = t->k; /* p like privileged */ |
1852 | jermar | 160 | data.w = ro ? false : t->w; |
161 | data.g = t->g; |
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2141 | jermar | 162 | |
1852 | jermar | 163 | dtlb_data_in_write(data.value); |
1851 | jermar | 164 | } |
165 | |||
1891 | jermar | 166 | /** Copy PTE to ITLB. |
167 | * |
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2141 | jermar | 168 | * @param t Page Table Entry to be copied. |
169 | * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. |
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1891 | jermar | 170 | */ |
2141 | jermar | 171 | void itlb_pte_copy(pte_t *t, index_t index) |
1852 | jermar | 172 | { |
173 | tlb_tag_access_reg_t tag; |
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174 | tlb_data_t data; |
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175 | page_address_t pg; |
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176 | frame_address_t fr; |
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177 | |||
2141 | jermar | 178 | pg.address = t->page + (index << MMU_PAGE_WIDTH); |
179 | fr.address = t->frame + (index << MMU_PAGE_WIDTH); |
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1852 | jermar | 180 | |
181 | tag.value = 0; |
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182 | tag.context = t->as->asid; |
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183 | tag.vpn = pg.vpn; |
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184 | |||
185 | itlb_tag_access_write(tag.value); |
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186 | |||
187 | data.value = 0; |
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188 | data.v = true; |
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189 | data.size = PAGESIZE_8K; |
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190 | data.pfn = fr.pfn; |
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191 | data.l = false; |
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192 | data.cp = t->c; |
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1864 | jermar | 193 | data.p = t->k; /* p like privileged */ |
1852 | jermar | 194 | data.w = false; |
195 | data.g = t->g; |
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196 | |||
197 | itlb_data_in_write(data.value); |
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198 | } |
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199 | |||
863 | jermar | 200 | /** ITLB miss handler. */ |
1851 | jermar | 201 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
863 | jermar | 202 | { |
1852 | jermar | 203 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
2141 | jermar | 204 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
1852 | jermar | 205 | pte_t *t; |
206 | |||
207 | page_table_lock(AS, true); |
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208 | t = page_mapping_find(AS, va); |
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209 | if (t && PTE_EXECUTABLE(t)) { |
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210 | /* |
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211 | * The mapping was found in the software page hash table. |
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212 | * Insert it into ITLB. |
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213 | */ |
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214 | t->a = true; |
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2141 | jermar | 215 | itlb_pte_copy(t, index); |
1891 | jermar | 216 | #ifdef CONFIG_TSB |
2141 | jermar | 217 | itsb_pte_copy(t, index); |
1891 | jermar | 218 | #endif |
1852 | jermar | 219 | page_table_unlock(AS, true); |
220 | } else { |
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221 | /* |
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2048 | jermar | 222 | * Forward the page fault to the address space page fault |
223 | * handler. |
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1852 | jermar | 224 | */ |
225 | page_table_unlock(AS, true); |
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226 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
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2048 | jermar | 227 | do_fast_instruction_access_mmu_miss_fault(istate, |
2141 | jermar | 228 | __FUNCTION__); |
1852 | jermar | 229 | } |
230 | } |
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863 | jermar | 231 | } |
232 | |||
1851 | jermar | 233 | /** DTLB miss handler. |
234 | * |
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2048 | jermar | 235 | * Note that some faults (e.g. kernel faults) were already resolved by the |
236 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
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1851 | jermar | 237 | */ |
238 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
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863 | jermar | 239 | { |
877 | jermar | 240 | tlb_tag_access_reg_t tag; |
1851 | jermar | 241 | uintptr_t va; |
2141 | jermar | 242 | index_t index; |
1851 | jermar | 243 | pte_t *t; |
883 | jermar | 244 | |
877 | jermar | 245 | tag.value = dtlb_tag_access_read(); |
2141 | jermar | 246 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
247 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
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1865 | jermar | 248 | |
1851 | jermar | 249 | if (tag.context == ASID_KERNEL) { |
250 | if (!tag.vpn) { |
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251 | /* NULL access in kernel */ |
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2048 | jermar | 252 | do_fast_data_access_mmu_miss_fault(istate, tag, |
2141 | jermar | 253 | __FUNCTION__); |
1851 | jermar | 254 | } |
2048 | jermar | 255 | do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected " |
2141 | jermar | 256 | "kernel page fault."); |
1851 | jermar | 257 | } |
873 | jermar | 258 | |
1851 | jermar | 259 | page_table_lock(AS, true); |
260 | t = page_mapping_find(AS, va); |
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261 | if (t) { |
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262 | /* |
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263 | * The mapping was found in the software page hash table. |
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264 | * Insert it into DTLB. |
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265 | */ |
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1852 | jermar | 266 | t->a = true; |
2141 | jermar | 267 | dtlb_pte_copy(t, index, true); |
1891 | jermar | 268 | #ifdef CONFIG_TSB |
2141 | jermar | 269 | dtsb_pte_copy(t, index, true); |
1891 | jermar | 270 | #endif |
1851 | jermar | 271 | page_table_unlock(AS, true); |
272 | } else { |
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273 | /* |
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2141 | jermar | 274 | * Forward the page fault to the address space page fault |
275 | * handler. |
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1851 | jermar | 276 | */ |
277 | page_table_unlock(AS, true); |
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278 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
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2048 | jermar | 279 | do_fast_data_access_mmu_miss_fault(istate, tag, |
2141 | jermar | 280 | __FUNCTION__); |
1851 | jermar | 281 | } |
877 | jermar | 282 | } |
863 | jermar | 283 | } |
284 | |||
285 | /** DTLB protection fault handler. */ |
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1851 | jermar | 286 | void fast_data_access_protection(int n, istate_t *istate) |
863 | jermar | 287 | { |
1859 | jermar | 288 | tlb_tag_access_reg_t tag; |
289 | uintptr_t va; |
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2141 | jermar | 290 | index_t index; |
1859 | jermar | 291 | pte_t *t; |
292 | |||
293 | tag.value = dtlb_tag_access_read(); |
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2141 | jermar | 294 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
295 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
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1859 | jermar | 296 | |
297 | page_table_lock(AS, true); |
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298 | t = page_mapping_find(AS, va); |
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299 | if (t && PTE_WRITABLE(t)) { |
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300 | /* |
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2048 | jermar | 301 | * The mapping was found in the software page hash table and is |
302 | * writable. Demap the old mapping and insert an updated mapping |
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303 | * into DTLB. |
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1859 | jermar | 304 | */ |
305 | t->a = true; |
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306 | t->d = true; |
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2141 | jermar | 307 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, |
308 | va + index * MMU_PAGE_SIZE); |
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309 | dtlb_pte_copy(t, index, false); |
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1891 | jermar | 310 | #ifdef CONFIG_TSB |
2141 | jermar | 311 | dtsb_pte_copy(t, index, false); |
1891 | jermar | 312 | #endif |
1859 | jermar | 313 | page_table_unlock(AS, true); |
314 | } else { |
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315 | /* |
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2048 | jermar | 316 | * Forward the page fault to the address space page fault |
317 | * handler. |
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1859 | jermar | 318 | */ |
319 | page_table_unlock(AS, true); |
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320 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
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2048 | jermar | 321 | do_fast_data_access_protection_fault(istate, tag, |
2141 | jermar | 322 | __FUNCTION__); |
1859 | jermar | 323 | } |
324 | } |
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863 | jermar | 325 | } |
326 | |||
570 | jermar | 327 | /** Print contents of both TLBs. */ |
328 | void tlb_print(void) |
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329 | { |
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330 | int i; |
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331 | tlb_data_t d; |
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332 | tlb_tag_read_reg_t t; |
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333 | |||
334 | printf("I-TLB contents:\n"); |
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335 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
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336 | d.value = itlb_data_access_read(i); |
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613 | jermar | 337 | t.value = itlb_tag_read_read(i); |
2078 | jermar | 338 | |
2048 | jermar | 339 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
2141 | jermar | 340 | "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, " |
341 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
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342 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, |
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343 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
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570 | jermar | 344 | } |
345 | |||
346 | printf("D-TLB contents:\n"); |
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347 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
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348 | d.value = dtlb_data_access_read(i); |
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613 | jermar | 349 | t.value = dtlb_tag_read_read(i); |
570 | jermar | 350 | |
2048 | jermar | 351 | printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " |
2141 | jermar | 352 | "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, " |
353 | "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn, |
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354 | t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, |
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355 | d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); |
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570 | jermar | 356 | } |
357 | |||
358 | } |
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617 | jermar | 359 | |
2141 | jermar | 360 | void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, |
361 | const char *str) |
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1852 | jermar | 362 | { |
1870 | jermar | 363 | fault_if_from_uspace(istate, "%s\n", str); |
1880 | jermar | 364 | dump_istate(istate); |
1852 | jermar | 365 | panic("%s\n", str); |
366 | } |
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367 | |||
2141 | jermar | 368 | void do_fast_data_access_mmu_miss_fault(istate_t *istate, |
369 | tlb_tag_access_reg_t tag, const char *str) |
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1851 | jermar | 370 | { |
371 | uintptr_t va; |
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372 | |||
2141 | jermar | 373 | va = tag.vpn << MMU_PAGE_WIDTH; |
1851 | jermar | 374 | |
2048 | jermar | 375 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
2141 | jermar | 376 | tag.context); |
1880 | jermar | 377 | dump_istate(istate); |
1851 | jermar | 378 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
379 | panic("%s\n", str); |
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380 | } |
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381 | |||
2141 | jermar | 382 | void do_fast_data_access_protection_fault(istate_t *istate, |
383 | tlb_tag_access_reg_t tag, const char *str) |
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1859 | jermar | 384 | { |
385 | uintptr_t va; |
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386 | |||
2141 | jermar | 387 | va = tag.vpn << MMU_PAGE_WIDTH; |
1859 | jermar | 388 | |
2048 | jermar | 389 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
2141 | jermar | 390 | tag.context); |
1859 | jermar | 391 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
1880 | jermar | 392 | dump_istate(istate); |
1859 | jermar | 393 | panic("%s\n", str); |
394 | } |
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395 | |||
1946 | jermar | 396 | void dump_sfsr_and_sfar(void) |
397 | { |
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398 | tlb_sfsr_reg_t sfsr; |
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399 | uintptr_t sfar; |
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400 | |||
401 | sfsr.value = dtlb_sfsr_read(); |
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402 | sfar = dtlb_sfar_read(); |
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403 | |||
2048 | jermar | 404 | printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
2141 | jermar | 405 | "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
406 | sfsr.ow, sfsr.fv); |
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1946 | jermar | 407 | printf("DTLB SFAR: address=%p\n", sfar); |
408 | |||
409 | dtlb_sfsr_write(0); |
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410 | } |
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411 | |||
617 | jermar | 412 | /** Invalidate all unlocked ITLB and DTLB entries. */ |
413 | void tlb_invalidate_all(void) |
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414 | { |
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415 | int i; |
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416 | tlb_data_t d; |
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417 | tlb_tag_read_reg_t t; |
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418 | |||
2078 | jermar | 419 | /* |
420 | * Walk all ITLB and DTLB entries and remove all unlocked mappings. |
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421 | * |
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422 | * The kernel doesn't use global mappings so any locked global mappings |
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423 | * found must have been created by someone else. Their only purpose now |
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424 | * is to collide with proper mappings. Invalidate immediately. It should |
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425 | * be safe to invalidate them as late as now. |
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426 | */ |
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427 | |||
617 | jermar | 428 | for (i = 0; i < ITLB_ENTRY_COUNT; i++) { |
429 | d.value = itlb_data_access_read(i); |
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2078 | jermar | 430 | if (!d.l || d.g) { |
617 | jermar | 431 | t.value = itlb_tag_read_read(i); |
432 | d.v = false; |
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433 | itlb_tag_access_write(t.value); |
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434 | itlb_data_access_write(i, d.value); |
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435 | } |
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436 | } |
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437 | |||
438 | for (i = 0; i < DTLB_ENTRY_COUNT; i++) { |
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439 | d.value = dtlb_data_access_read(i); |
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2078 | jermar | 440 | if (!d.l || d.g) { |
617 | jermar | 441 | t.value = dtlb_tag_read_read(i); |
442 | d.v = false; |
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443 | dtlb_tag_access_write(t.value); |
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444 | dtlb_data_access_write(i, d.value); |
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445 | } |
||
446 | } |
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447 | |||
448 | } |
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449 | |||
2048 | jermar | 450 | /** Invalidate all ITLB and DTLB entries that belong to specified ASID |
451 | * (Context). |
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617 | jermar | 452 | * |
453 | * @param asid Address Space ID. |
||
454 | */ |
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455 | void tlb_invalidate_asid(asid_t asid) |
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456 | { |
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1865 | jermar | 457 | tlb_context_reg_t pc_save, ctx; |
1860 | jermar | 458 | |
1865 | jermar | 459 | /* switch to nucleus because we are mapped by the primary context */ |
460 | nucleus_enter(); |
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461 | |||
462 | ctx.v = pc_save.v = mmu_primary_context_read(); |
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1860 | jermar | 463 | ctx.context = asid; |
1865 | jermar | 464 | mmu_primary_context_write(ctx.v); |
1860 | jermar | 465 | |
1865 | jermar | 466 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
467 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); |
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1860 | jermar | 468 | |
1865 | jermar | 469 | mmu_primary_context_write(pc_save.v); |
470 | |||
471 | nucleus_leave(); |
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617 | jermar | 472 | } |
473 | |||
2048 | jermar | 474 | /** Invalidate all ITLB and DTLB entries for specified page range in specified |
475 | * address space. |
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617 | jermar | 476 | * |
477 | * @param asid Address Space ID. |
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727 | jermar | 478 | * @param page First page which to sweep out from ITLB and DTLB. |
479 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
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617 | jermar | 480 | */ |
1780 | jermar | 481 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
617 | jermar | 482 | { |
727 | jermar | 483 | int i; |
1865 | jermar | 484 | tlb_context_reg_t pc_save, ctx; |
727 | jermar | 485 | |
1865 | jermar | 486 | /* switch to nucleus because we are mapped by the primary context */ |
487 | nucleus_enter(); |
||
488 | |||
489 | ctx.v = pc_save.v = mmu_primary_context_read(); |
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1860 | jermar | 490 | ctx.context = asid; |
1865 | jermar | 491 | mmu_primary_context_write(ctx.v); |
1860 | jermar | 492 | |
2141 | jermar | 493 | for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) { |
2134 | jermar | 494 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
2141 | jermar | 495 | page + i * MMU_PAGE_SIZE); |
2134 | jermar | 496 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, |
2141 | jermar | 497 | page + i * MMU_PAGE_SIZE); |
727 | jermar | 498 | } |
1860 | jermar | 499 | |
1865 | jermar | 500 | mmu_primary_context_write(pc_save.v); |
501 | |||
502 | nucleus_leave(); |
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617 | jermar | 503 | } |
1702 | cejka | 504 | |
1792 | jermar | 505 | /** @} |
1702 | cejka | 506 | */ |