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418 | jermar | 1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #ifndef __sparc64_TLB_H__ |
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30 | #define __sparc64_TLB_H__ |
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31 | |||
530 | jermar | 32 | #include <arch/mm/tte.h> |
569 | jermar | 33 | #include <arch/asm.h> |
613 | jermar | 34 | #include <arch/barrier.h> |
569 | jermar | 35 | #include <arch/types.h> |
36 | #include <typedefs.h> |
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530 | jermar | 37 | |
569 | jermar | 38 | #define ITLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
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40 | |||
531 | jermar | 41 | /** I-MMU ASIs. */ |
42 | #define ASI_IMMU 0x50 |
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43 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
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44 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
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45 | #define ASI_ITLB_DATA_IN_REG 0x54 |
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46 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
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47 | #define ASI_ITLB_TAG_READ_REG 0x56 |
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48 | #define ASI_IMMU_DEMAP 0x57 |
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49 | |||
50 | /** Virtual Addresses within ASI_IMMU. */ |
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51 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
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52 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
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53 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
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54 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
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55 | |||
56 | /** D-MMU ASIs. */ |
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57 | #define ASI_DMMU 0x58 |
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58 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
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59 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
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60 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
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61 | #define ASI_DTLB_DATA_IN_REG 0x5c |
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62 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
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63 | #define ASI_DTLB_TAG_READ_REG 0x5e |
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64 | #define ASI_DMMU_DEMAP 0x5f |
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65 | |||
66 | /** Virtual Addresses within ASI_DMMU. */ |
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67 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
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68 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
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69 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
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70 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
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71 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
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72 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
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73 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
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74 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
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75 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
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76 | |||
530 | jermar | 77 | /** I-/D-TLB Data In/Access Register type. */ |
78 | typedef tte_data_t tlb_data_t; |
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79 | |||
569 | jermar | 80 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
81 | union tlb_data_access_addr { |
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82 | __u64 value; |
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83 | struct { |
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84 | __u64 : 55; |
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85 | unsigned tlb_entry : 6; |
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86 | unsigned : 3; |
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87 | } __attribute__ ((packed)); |
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88 | }; |
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89 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
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90 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
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418 | jermar | 91 | |
569 | jermar | 92 | /** I-/D-TLB Tag Read Register. */ |
93 | union tlb_tag_read_reg { |
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94 | __u64 value; |
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95 | struct { |
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96 | __u64 va : 51; /**< Virtual Address. */ |
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97 | unsigned context : 13; /**< Context identifier. */ |
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98 | } __attribute__ ((packed)); |
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99 | }; |
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100 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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613 | jermar | 101 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
569 | jermar | 102 | |
103 | /** Read IMMU TLB Data Access Register. |
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104 | * |
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105 | * @param entry TLB Entry index. |
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106 | * |
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107 | * @return Current value of specified IMMU TLB Data Access Register. |
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108 | */ |
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109 | static inline __u64 itlb_data_access_read(index_t entry) |
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110 | { |
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111 | tlb_data_access_addr_t reg; |
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112 | |||
113 | reg.value = 0; |
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114 | reg.tlb_entry = entry; |
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115 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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116 | } |
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117 | |||
118 | /** Read DMMU TLB Data Access Register. |
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119 | * |
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120 | * @param entry TLB Entry index. |
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121 | * |
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122 | * @return Current value of specified DMMU TLB Data Access Register. |
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123 | */ |
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124 | static inline __u64 dtlb_data_access_read(index_t entry) |
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125 | { |
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126 | tlb_data_access_addr_t reg; |
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127 | |||
128 | reg.value = 0; |
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129 | reg.tlb_entry = entry; |
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130 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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131 | } |
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132 | |||
133 | /** Read IMMU TLB Tag Read Register. |
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134 | * |
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135 | * @param entry TLB Entry index. |
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136 | * |
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137 | * @return Current value of specified IMMU TLB Tag Read Register. |
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138 | */ |
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613 | jermar | 139 | static inline __u64 itlb_tag_read_read(index_t entry) |
569 | jermar | 140 | { |
141 | tlb_tag_read_addr_t tag; |
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142 | |||
143 | tag.value = 0; |
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144 | tag.tlb_entry = entry; |
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145 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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146 | } |
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147 | |||
148 | /** Read DMMU TLB Tag Read Register. |
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149 | * |
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150 | * @param entry TLB Entry index. |
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151 | * |
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152 | * @return Current value of specified DMMU TLB Tag Read Register. |
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153 | */ |
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613 | jermar | 154 | static inline __u64 dtlb_tag_read_read(index_t entry) |
569 | jermar | 155 | { |
156 | tlb_tag_read_addr_t tag; |
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157 | |||
158 | tag.value = 0; |
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159 | tag.tlb_entry = entry; |
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160 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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161 | } |
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162 | |||
613 | jermar | 163 | /** Write IMMU TLB Tag Access Register. |
164 | * |
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165 | * @param v Value to be written. |
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166 | */ |
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167 | static inline void itlb_tag_access_write(__u64 v) |
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168 | { |
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169 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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170 | flush(); |
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171 | } |
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172 | |||
173 | /** Write DMMU TLB Tag Access Register. |
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174 | * |
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175 | * @param v Value to be written. |
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176 | */ |
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177 | static inline void dtlb_tag_access_write(__u64 v) |
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178 | { |
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179 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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180 | flush(); |
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181 | } |
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182 | |||
183 | /** Write IMMU TLB Data in Register. |
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184 | * |
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185 | * @param v Value to be written. |
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186 | */ |
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187 | static inline void itlb_data_in_write(__u64 v) |
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188 | { |
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189 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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190 | flush(); |
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191 | } |
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192 | |||
193 | /** Write DMMU TLB Data in Register. |
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194 | * |
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195 | * @param v Value to be written. |
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196 | */ |
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197 | static inline void dtlb_data_in_write(__u64 v) |
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198 | { |
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199 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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200 | flush(); |
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201 | } |
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202 | |||
418 | jermar | 203 | #endif |