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418 | jermar | 1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #ifndef __sparc64_ASM_H__ |
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30 | #define __sparc64_ASM_H__ |
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31 | |||
650 | jermar | 32 | #include <typedefs.h> |
418 | jermar | 33 | #include <arch/types.h> |
650 | jermar | 34 | #include <arch/register.h> |
418 | jermar | 35 | #include <config.h> |
36 | |||
650 | jermar | 37 | /** Read Processor State register. |
38 | * |
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39 | * @return Value of PSTATE register. |
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40 | */ |
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41 | static inline __u64 pstate_read(void) |
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42 | { |
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43 | __u64 v; |
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44 | |||
45 | __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
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46 | |||
47 | return v; |
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48 | } |
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49 | |||
50 | /** Write Processor State register. |
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51 | * |
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52 | * @param New value of PSTATE register. |
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53 | */ |
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54 | static inline void pstate_write(__u64 v) |
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55 | { |
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56 | __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
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57 | } |
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58 | |||
658 | jermar | 59 | /** Read TICK_compare Register. |
60 | * |
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61 | * @return Value of TICK_comapre register. |
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62 | */ |
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63 | static inline __u64 tick_compare_read(void) |
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64 | { |
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65 | __u64 v; |
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66 | |||
67 | __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
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68 | |||
69 | return v; |
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70 | } |
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650 | jermar | 71 | |
658 | jermar | 72 | /** Write TICK_compare Register. |
73 | * |
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74 | * @param New value of TICK_comapre register. |
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75 | */ |
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76 | static inline void tick_compare_write(__u64 v) |
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77 | { |
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78 | __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
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79 | } |
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80 | |||
81 | /** Read TICK Register. |
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82 | * |
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83 | * @return Value of TICK register. |
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84 | */ |
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85 | static inline __u64 tick_read(void) |
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86 | { |
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87 | __u64 v; |
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88 | |||
89 | __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
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90 | |||
91 | return v; |
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92 | } |
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93 | |||
94 | /** Write TICK Register. |
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95 | * |
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96 | * @param New value of TICK register. |
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97 | */ |
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98 | static inline void tick_write(__u64 v) |
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99 | { |
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100 | __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
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101 | } |
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102 | |||
664 | jermar | 103 | /** Read SOFTINT Register. |
104 | * |
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105 | * @return Value of SOFTINT register. |
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106 | */ |
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107 | static inline __u64 softint_read(void) |
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108 | { |
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109 | __u64 v; |
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658 | jermar | 110 | |
664 | jermar | 111 | __asm__ volatile ("rd %%softint, %0\n" : "=r" (v)); |
112 | |||
113 | return v; |
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114 | } |
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115 | |||
116 | /** Write SOFTINT Register. |
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117 | * |
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118 | * @param New value of SOFTINT register. |
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119 | */ |
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120 | static inline void softint_write(__u64 v) |
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121 | { |
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122 | __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
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123 | } |
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124 | |||
665 | jermar | 125 | /** Write CLEAR_SOFTINT Register. |
126 | * |
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127 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
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128 | * |
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129 | * @param New value of CLEAR_SOFTINT register. |
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130 | */ |
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131 | static inline void clear_softint_write(__u64 v) |
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132 | { |
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133 | __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
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134 | } |
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135 | |||
418 | jermar | 136 | /** Enable interrupts. |
137 | * |
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138 | * Enable interrupts and return previous |
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139 | * value of IPL. |
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140 | * |
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141 | * @return Old interrupt priority level. |
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142 | */ |
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143 | static inline ipl_t interrupts_enable(void) { |
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650 | jermar | 144 | pstate_reg_t pstate; |
145 | __u64 value; |
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146 | |||
147 | value = pstate_read(); |
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148 | pstate.value = value; |
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149 | pstate.ie = true; |
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150 | pstate_write(pstate.value); |
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151 | |||
152 | return (ipl_t) value; |
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418 | jermar | 153 | } |
154 | |||
155 | /** Disable interrupts. |
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156 | * |
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157 | * Disable interrupts and return previous |
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158 | * value of IPL. |
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159 | * |
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160 | * @return Old interrupt priority level. |
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161 | */ |
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162 | static inline ipl_t interrupts_disable(void) { |
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650 | jermar | 163 | pstate_reg_t pstate; |
164 | __u64 value; |
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165 | |||
166 | value = pstate_read(); |
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167 | pstate.value = value; |
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168 | pstate.ie = false; |
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169 | pstate_write(pstate.value); |
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170 | |||
171 | return (ipl_t) value; |
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418 | jermar | 172 | } |
173 | |||
174 | /** Restore interrupt priority level. |
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175 | * |
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176 | * Restore IPL. |
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177 | * |
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178 | * @param ipl Saved interrupt priority level. |
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179 | */ |
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180 | static inline void interrupts_restore(ipl_t ipl) { |
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650 | jermar | 181 | pstate_reg_t pstate; |
182 | |||
183 | pstate.value = pstate_read(); |
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184 | pstate.ie = ((pstate_reg_t) ipl).ie; |
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185 | pstate_write(pstate.value); |
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418 | jermar | 186 | } |
187 | |||
188 | /** Return interrupt priority level. |
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189 | * |
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190 | * Return IPL. |
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191 | * |
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192 | * @return Current interrupt priority level. |
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193 | */ |
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194 | static inline ipl_t interrupts_read(void) { |
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650 | jermar | 195 | return (ipl_t) pstate_read(); |
418 | jermar | 196 | } |
197 | |||
198 | /** Return base address of current stack. |
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199 | * |
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200 | * Return the base address of the current stack. |
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201 | * The stack is assumed to be STACK_SIZE bytes long. |
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202 | * The stack must start on page boundary. |
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203 | */ |
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204 | static inline __address get_stack_base(void) |
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205 | { |
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426 | jermar | 206 | __address v; |
207 | |||
650 | jermar | 208 | __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
426 | jermar | 209 | |
210 | return v; |
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418 | jermar | 211 | } |
212 | |||
640 | jermar | 213 | /** Read Version Register. |
214 | * |
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215 | * @return Value of VER register. |
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216 | */ |
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217 | static inline __u64 ver_read(void) |
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218 | { |
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219 | __u64 v; |
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220 | |||
221 | __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
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222 | |||
223 | return v; |
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224 | } |
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225 | |||
529 | jermar | 226 | /** Read Trap Base Address register. |
227 | * |
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228 | * @return Current value in TBA. |
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229 | */ |
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230 | static inline __u64 tba_read(void) |
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231 | { |
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232 | __u64 v; |
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233 | |||
234 | __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
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235 | |||
236 | return v; |
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237 | } |
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238 | |||
239 | /** Write Trap Base Address register. |
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240 | * |
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241 | * @param New value of TBA. |
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242 | */ |
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243 | static inline void tba_write(__u64 v) |
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244 | { |
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245 | __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
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246 | } |
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247 | |||
569 | jermar | 248 | /** Load __u64 from alternate space. |
249 | * |
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250 | * @param asi ASI determining the alternate space. |
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251 | * @param va Virtual address within the ASI. |
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252 | * |
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253 | * @return Value read from the virtual address in the specified address space. |
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254 | */ |
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255 | static inline __u64 asi_u64_read(asi_t asi, __address va) |
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256 | { |
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257 | __u64 v; |
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258 | |||
259 | __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi)); |
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260 | |||
261 | return v; |
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262 | } |
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529 | jermar | 263 | |
569 | jermar | 264 | /** Store __u64 to alternate space. |
265 | * |
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266 | * @param asi ASI determining the alternate space. |
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267 | * @param va Virtual address within the ASI. |
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268 | * @param v Value to be written. |
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269 | */ |
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270 | static inline void asi_u64_write(asi_t asi, __address va, __u64 v) |
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271 | { |
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613 | jermar | 272 | __asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory"); |
569 | jermar | 273 | } |
274 | |||
658 | jermar | 275 | |
276 | |||
418 | jermar | 277 | void cpu_halt(void); |
278 | void cpu_sleep(void); |
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279 | void asm_delay_loop(__u32 t); |
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280 | |||
281 | #endif |