Rev 445 | Rev 470 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
212 | vana | 1 | # |
2 | # Copyright (C) 2005 Jakub Vana |
||
3 | # All rights reserved. |
||
4 | # |
||
5 | # Redistribution and use in source and binary forms, with or without |
||
6 | # modification, are permitted provided that the following conditions |
||
7 | # are met: |
||
8 | # |
||
9 | # - Redistributions of source code must retain the above copyright |
||
10 | # notice, this list of conditions and the following disclaimer. |
||
11 | # - Redistributions in binary form must reproduce the above copyright |
||
12 | # notice, this list of conditions and the following disclaimer in the |
||
13 | # documentation and/or other materials provided with the distribution. |
||
14 | # - The name of the author may not be used to endorse or promote products |
||
15 | # derived from this software without specific prior written permission. |
||
16 | # |
||
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
27 | # |
||
28 | |||
443 | jermar | 29 | #include <arch/stack.h> |
212 | vana | 30 | |
443 | jermar | 31 | #define STACK_ITEMS 12 |
32 | #define STACK_FRAME_SIZE ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE) |
||
33 | |||
34 | #if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0) |
||
35 | #error Memory stack must be 16-byte aligned. |
||
36 | #endif |
||
37 | |||
438 | jermar | 38 | /** Heavyweight interrupt handler |
39 | * |
||
435 | jermar | 40 | * This macro roughly follows steps from 1 to 19 described in |
41 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
||
42 | * |
||
438 | jermar | 43 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions). |
44 | * This goal is achieved by using procedure calls after RSE becomes operational. |
||
45 | * |
||
435 | jermar | 46 | * Some steps are skipped (enabling and disabling interrupts). |
47 | * Some steps are not fully supported yet (e.g. interruptions |
||
438 | jermar | 48 | * from userspace and floating-point context). |
456 | jermar | 49 | * |
50 | * @param offs Offset from the beginning of IVT. |
||
51 | * @param handler Interrupt handler address. |
||
435 | jermar | 52 | */ |
53 | .macro HEAVYWEIGHT_HANDLER offs handler |
||
54 | .org IVT + \offs |
||
212 | vana | 55 | |
435 | jermar | 56 | /* 1. copy interrupt registers into bank 0 */ |
57 | mov r24 = cr.iip |
||
58 | mov r25 = cr.ipsr |
||
59 | mov r26 = cr.iipa |
||
60 | mov r27 = cr.isr |
||
61 | mov r28 = cr.ifa |
||
62 | |||
63 | /* 2. preserve predicate register into bank 0 */ |
||
64 | mov r29 = pr ;; |
||
65 | |||
438 | jermar | 66 | /* 3. switch to kernel memory stack */ |
435 | jermar | 67 | /* TODO: support interruptions from userspace */ |
68 | /* assume kernel stack */ |
||
69 | |||
439 | jermar | 70 | /* 4. save registers in bank 0 into memory stack */ |
443 | jermar | 71 | add r31 = -8, r12 ;; |
72 | add r12 = -STACK_FRAME_SIZE, r12 ;; |
||
441 | jermar | 73 | |
443 | jermar | 74 | st8 [r31] = r29, -8 ;; /* save predicate registers */ |
438 | jermar | 75 | |
443 | jermar | 76 | st8 [r31] = r24, -8 ;; /* save cr.iip */ |
77 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */ |
||
78 | st8 [r31] = r26, -8 ;; /* save cr.iipa */ |
||
79 | st8 [r31] = r27, -8 ;; /* save cr.isr */ |
||
80 | st8 [r31] = r28, -8 ;; /* save cr.ifa */ |
||
438 | jermar | 81 | |
82 | /* 5. RSE switch from interrupted context */ |
||
435 | jermar | 83 | .auto |
84 | mov r24 = ar.rsc |
||
85 | mov r25 = ar.pfs |
||
86 | cover |
||
87 | mov r26 = cr.ifs |
||
88 | |||
443 | jermar | 89 | st8 [r31] = r24, -8 /* save ar.rsc */ |
90 | st8 [r31] = r25, -8 /* save ar.pfs */ |
||
91 | st8 [r31] = r26, -8 /* save ar.ifs */ |
||
435 | jermar | 92 | |
93 | and r30 = ~3, r24 |
||
94 | mov ar.rsc = r30 /* place RSE in enforced lazy mode */ |
||
95 | |||
96 | mov r27 = ar.rnat |
||
97 | mov r28 = ar.bspstore |
||
98 | |||
99 | /* assume kernel backing store */ |
||
100 | mov ar.bspstore = r28 |
||
101 | |||
102 | mov r29 = ar.bsp |
||
103 | |||
443 | jermar | 104 | st8 [r31] = r27, -8 /* save ar.rnat */ |
105 | st8 [r31] = r28, -8 /* save ar.bspstore */ |
||
456 | jermar | 106 | st8 [r31] = r29, -8 /* save ar.bsp */ |
435 | jermar | 107 | |
108 | mov ar.rsc = r24 /* restore RSE's setting */ |
||
109 | .explicit |
||
110 | |||
438 | jermar | 111 | /* the rest of the save-handler can be kept outside IVT */ |
112 | |||
113 | movl r24 = \handler |
||
114 | mov r25 = b0 |
||
115 | br.call.sptk.many rp = heavyweight_handler_inner |
||
116 | 0: mov b0 = r25 |
||
117 | |||
439 | jermar | 118 | br heavyweight_handler_finalize |
438 | jermar | 119 | .endm |
120 | |||
121 | .global heavyweight_handler_inner |
||
122 | heavyweight_handler_inner: |
||
123 | /* |
||
124 | * From this point, the rest of the interrupted context |
||
125 | * will be preserved in stacked registers and backing store. |
||
126 | */ |
||
127 | alloc loc0 = ar.pfs, 0, 46, 0, 0 ;; |
||
128 | |||
129 | /* copy handler address (r24 from bank 0 will be invisible soon) */ |
||
130 | mov loc1 = r24 |
||
131 | |||
435 | jermar | 132 | /* 6. switch to bank 1 and reenable PSR.ic */ |
133 | ssm 0x2000 |
||
134 | bsw.1 ;; |
||
135 | srlz.d |
||
136 | |||
137 | /* 7. preserve branch and application registers */ |
||
438 | jermar | 138 | mov loc2 = ar.unat |
139 | mov loc3 = ar.lc |
||
140 | mov loc4 = ar.ec |
||
141 | mov loc5 = ar.ccv |
||
142 | mov loc6 = ar.csd |
||
143 | mov loc7 = ar.ssd |
||
435 | jermar | 144 | |
438 | jermar | 145 | mov loc8 = b0 |
146 | mov loc9 = b1 |
||
147 | mov loc10 = b2 |
||
148 | mov loc11 = b3 |
||
149 | mov loc12 = b4 |
||
150 | mov loc13 = b5 |
||
151 | mov loc14 = b6 |
||
152 | mov loc15 = b7 |
||
153 | |||
435 | jermar | 154 | /* 8. preserve general and floating-point registers */ |
155 | /* TODO: save floating-point context */ |
||
438 | jermar | 156 | mov loc16 = r1 |
157 | mov loc17 = r2 |
||
158 | mov loc18 = r3 |
||
159 | mov loc19 = r4 |
||
160 | mov loc20 = r5 |
||
161 | mov loc21 = r6 |
||
162 | mov loc22 = r7 |
||
163 | mov loc23 = r8 |
||
164 | mov loc24 = r9 |
||
165 | mov loc25 = r10 |
||
166 | mov loc26 = r11 |
||
167 | /* skip r12 (stack pointer) */ |
||
168 | mov loc27 = r13 |
||
169 | mov loc28 = r14 |
||
170 | mov loc29 = r15 |
||
171 | mov loc30 = r16 |
||
172 | mov loc31 = r17 |
||
173 | mov loc32 = r18 |
||
174 | mov loc33 = r19 |
||
175 | mov loc34 = r20 |
||
176 | mov loc35 = r21 |
||
177 | mov loc36 = r22 |
||
178 | mov loc37 = r23 |
||
179 | mov loc38 = r24 |
||
180 | mov loc39 = r25 |
||
181 | mov loc40 = r26 |
||
182 | mov loc41 = r27 |
||
183 | mov loc42 = r28 |
||
184 | mov loc43 = r29 |
||
185 | mov loc44 = r30 |
||
186 | mov loc45 = r31 |
||
187 | |||
435 | jermar | 188 | /* 9. skipped (will not enable interrupts) */ |
238 | vana | 189 | |
438 | jermar | 190 | /* 10. call handler */ |
191 | mov b1 = loc1 |
||
192 | br.call.sptk.many b0 = b1 |
||
193 | |||
194 | /* 11. return from handler */ |
||
195 | 0: |
||
196 | |||
435 | jermar | 197 | /* 12. skipped (will not disable interrupts) */ |
438 | jermar | 198 | |
435 | jermar | 199 | /* 13. restore general and floating-point registers */ |
200 | /* TODO: restore floating-point context */ |
||
438 | jermar | 201 | mov r1 = loc16 |
202 | mov r2 = loc17 |
||
203 | mov r3 = loc18 |
||
204 | mov r4 = loc19 |
||
205 | mov r5 = loc20 |
||
206 | mov r6 = loc21 |
||
207 | mov r7 = loc22 |
||
208 | mov r8 = loc23 |
||
209 | mov r9 = loc24 |
||
210 | mov r10 = loc25 |
||
211 | mov r11 = loc26 |
||
212 | /* skip r12 (stack pointer) */ |
||
213 | mov r13 = loc27 |
||
214 | mov r14 = loc28 |
||
215 | mov r15 = loc29 |
||
216 | mov r16 = loc30 |
||
217 | mov r17 = loc31 |
||
218 | mov r18 = loc32 |
||
219 | mov r19 = loc33 |
||
220 | mov r20 = loc34 |
||
221 | mov r21 = loc35 |
||
222 | mov r22 = loc36 |
||
223 | mov r23 = loc37 |
||
224 | mov r24 = loc38 |
||
225 | mov r25 = loc39 |
||
226 | mov r26 = loc40 |
||
227 | mov r27 = loc41 |
||
228 | mov r28 = loc42 |
||
229 | mov r29 = loc43 |
||
230 | mov r30 = loc44 |
||
231 | mov r31 = loc45 |
||
435 | jermar | 232 | |
233 | /* 14. restore branch and application registers */ |
||
438 | jermar | 234 | mov ar.unat = loc2 |
235 | mov ar.lc = loc3 |
||
236 | mov ar.ec = loc4 |
||
237 | mov ar.ccv = loc5 |
||
238 | mov ar.csd = loc6 |
||
239 | mov ar.ssd = loc7 |
||
435 | jermar | 240 | |
438 | jermar | 241 | mov b0 = loc8 |
242 | mov b1 = loc9 |
||
243 | mov b2 = loc10 |
||
244 | mov b3 = loc11 |
||
245 | mov b4 = loc12 |
||
246 | mov b5 = loc13 |
||
247 | mov b6 = loc14 |
||
248 | mov b7 = loc15 |
||
249 | |||
435 | jermar | 250 | /* 15. disable PSR.ic and switch to bank 0 */ |
251 | rsm 0x2000 |
||
252 | bsw.0 ;; |
||
253 | srlz.d |
||
438 | jermar | 254 | |
255 | mov ar.pfs = loc0 |
||
256 | br.ret.sptk.many rp |
||
257 | |||
258 | .global heavyweight_handler_finalize |
||
259 | heavyweight_handler_finalize: |
||
260 | /* 16. RSE switch to interrupted context */ |
||
444 | vana | 261 | .auto |
456 | jermar | 262 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
444 | vana | 263 | |
445 | jermar | 264 | add r31 = STACK_SCRATCH_AREA_SIZE, r12 |
444 | vana | 265 | |
456 | jermar | 266 | mov r28 = ar.bspstore /* calculate loadrs (step 2) */ |
267 | ld8 r29 = [r31], +8 /* load ar.bsp */ |
||
444 | vana | 268 | sub r27 = r29 , r28 |
269 | shl r27 = r27, 16 |
||
270 | |||
271 | mov r24 = ar.rsc |
||
272 | and r30 = ~3, r24 |
||
273 | or r24 = r30 , r27 |
||
274 | mov ar.rsc = r24 /* place RSE in enforced lazy mode */ |
||
275 | |||
456 | jermar | 276 | loadrs /* (step 3) */ |
444 | vana | 277 | |
456 | jermar | 278 | ld8 r28 = [r31], +8 /* load ar.bspstore */ |
279 | ld8 r27 = [r31], +8 /* load ar.rnat */ |
||
280 | ld8 r26 = [r31], +8 /* load cr.ifs */ |
||
281 | ld8 r25 = [r31], +8 /* load ar.pfs */ |
||
282 | ld8 r24 = [r31], +8 /* load ar.rsc */ |
||
444 | vana | 283 | |
456 | jermar | 284 | mov ar.bspstore = r28 /* (step 4) */ |
285 | mov ar.rnat = r27 /* (step 5) */ |
||
444 | vana | 286 | |
456 | jermar | 287 | mov ar.pfs = r25 /* (step 6) */ |
444 | vana | 288 | mov cr.ifs = r26 |
289 | |||
456 | jermar | 290 | mov ar.rsc = r24 /* (step 7) */ |
444 | vana | 291 | .explicit |
292 | |||
435 | jermar | 293 | /* 17. restore interruption state from memory stack */ |
456 | jermar | 294 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */ |
295 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
||
296 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
||
297 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
||
298 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
||
444 | vana | 299 | |
300 | mov cr.iip = r24 |
||
301 | mov cr.ipsr = r25 |
||
302 | mov cr.iipa = r26 |
||
303 | mov cr.isr = r27 |
||
304 | mov cr.ifa = r28 |
||
305 | |||
435 | jermar | 306 | /* 18. restore predicate registers from memory stack */ |
444 | vana | 307 | ld8 r29 = [r31] , -8 ;; /* load predicate registers */ |
456 | jermar | 308 | mov pr = r29 |
435 | jermar | 309 | |
310 | /* 19. return from interruption */ |
||
456 | jermar | 311 | add r12 = STACK_FRAME_SIZE, r12 |
312 | rfi ;; |
||
435 | jermar | 313 | |
238 | vana | 314 | dump_gregs: |
315 | mov r16 = REG_DUMP;; |
||
316 | st8 [r16] = r0;; |
||
317 | add r16 = 8,r16 ;; |
||
318 | st8 [r16] = r1;; |
||
319 | add r16 = 8,r16 ;; |
||
320 | st8 [r16] = r2;; |
||
321 | add r16 = 8,r16 ;; |
||
322 | st8 [r16] = r3;; |
||
323 | add r16 = 8,r16 ;; |
||
324 | st8 [r16] = r4;; |
||
325 | add r16 = 8,r16 ;; |
||
326 | st8 [r16] = r5;; |
||
327 | add r16 = 8,r16 ;; |
||
328 | st8 [r16] = r6;; |
||
329 | add r16 = 8,r16 ;; |
||
330 | st8 [r16] = r7;; |
||
331 | add r16 = 8,r16 ;; |
||
332 | st8 [r16] = r8;; |
||
333 | add r16 = 8,r16 ;; |
||
334 | st8 [r16] = r9;; |
||
335 | add r16 = 8,r16 ;; |
||
336 | st8 [r16] = r10;; |
||
337 | add r16 = 8,r16 ;; |
||
338 | st8 [r16] = r11;; |
||
339 | add r16 = 8,r16 ;; |
||
340 | st8 [r16] = r12;; |
||
341 | add r16 = 8,r16 ;; |
||
342 | st8 [r16] = r13;; |
||
343 | add r16 = 8,r16 ;; |
||
344 | st8 [r16] = r14;; |
||
345 | add r16 = 8,r16 ;; |
||
346 | st8 [r16] = r15;; |
||
347 | add r16 = 8,r16 ;; |
||
348 | |||
349 | bsw.1;; |
||
350 | mov r15 = r16;; |
||
351 | bsw.0;; |
||
352 | st8 [r16] = r15;; |
||
353 | add r16 = 8,r16 ;; |
||
354 | bsw.1;; |
||
355 | mov r15 = r17;; |
||
356 | bsw.0;; |
||
357 | st8 [r16] = r15;; |
||
358 | add r16 = 8,r16 ;; |
||
359 | bsw.1;; |
||
360 | mov r15 = r18;; |
||
361 | bsw.0;; |
||
362 | st8 [r16] = r15;; |
||
363 | add r16 = 8,r16 ;; |
||
364 | bsw.1;; |
||
365 | mov r15 = r19;; |
||
366 | bsw.0;; |
||
367 | st8 [r16] = r15;; |
||
368 | add r16 = 8,r16 ;; |
||
369 | bsw.1;; |
||
370 | mov r15 = r20;; |
||
371 | bsw.0;; |
||
372 | st8 [r16] = r15;; |
||
373 | add r16 = 8,r16 ;; |
||
374 | bsw.1;; |
||
375 | mov r15 = r21;; |
||
376 | bsw.0;; |
||
377 | st8 [r16] = r15;; |
||
378 | add r16 = 8,r16 ;; |
||
379 | bsw.1;; |
||
380 | mov r15 = r22;; |
||
381 | bsw.0;; |
||
382 | st8 [r16] = r15;; |
||
383 | add r16 = 8,r16 ;; |
||
384 | bsw.1;; |
||
385 | mov r15 = r23;; |
||
386 | bsw.0;; |
||
387 | st8 [r16] = r15;; |
||
388 | add r16 = 8,r16 ;; |
||
389 | bsw.1;; |
||
390 | mov r15 = r24;; |
||
391 | bsw.0;; |
||
392 | st8 [r16] = r15;; |
||
393 | add r16 = 8,r16 ;; |
||
394 | bsw.1;; |
||
395 | mov r15 = r25;; |
||
396 | bsw.0;; |
||
397 | st8 [r16] = r15;; |
||
398 | add r16 = 8,r16 ;; |
||
399 | bsw.1;; |
||
400 | mov r15 = r26;; |
||
401 | bsw.0;; |
||
402 | st8 [r16] = r15;; |
||
403 | add r16 = 8,r16 ;; |
||
404 | bsw.1;; |
||
405 | mov r15 = r27;; |
||
406 | bsw.0;; |
||
407 | st8 [r16] = r15;; |
||
408 | add r16 = 8,r16 ;; |
||
409 | bsw.1;; |
||
410 | mov r15 = r28;; |
||
411 | bsw.0;; |
||
412 | st8 [r16] = r15;; |
||
413 | add r16 = 8,r16 ;; |
||
414 | bsw.1;; |
||
415 | mov r15 = r29;; |
||
416 | bsw.0;; |
||
417 | st8 [r16] = r15;; |
||
418 | add r16 = 8,r16 ;; |
||
419 | bsw.1;; |
||
420 | mov r15 = r30;; |
||
421 | bsw.0;; |
||
422 | st8 [r16] = r15;; |
||
423 | add r16 = 8,r16 ;; |
||
424 | bsw.1;; |
||
425 | mov r15 = r31;; |
||
426 | bsw.0;; |
||
427 | st8 [r16] = r15;; |
||
428 | add r16 = 8,r16 ;; |
||
429 | |||
430 | |||
431 | st8 [r16] = r32;; |
||
432 | add r16 = 8,r16 ;; |
||
433 | st8 [r16] = r33;; |
||
434 | add r16 = 8,r16 ;; |
||
435 | st8 [r16] = r34;; |
||
436 | add r16 = 8,r16 ;; |
||
437 | st8 [r16] = r35;; |
||
438 | add r16 = 8,r16 ;; |
||
439 | st8 [r16] = r36;; |
||
440 | add r16 = 8,r16 ;; |
||
441 | st8 [r16] = r37;; |
||
442 | add r16 = 8,r16 ;; |
||
443 | st8 [r16] = r38;; |
||
444 | add r16 = 8,r16 ;; |
||
445 | st8 [r16] = r39;; |
||
446 | add r16 = 8,r16 ;; |
||
447 | st8 [r16] = r40;; |
||
448 | add r16 = 8,r16 ;; |
||
449 | st8 [r16] = r41;; |
||
450 | add r16 = 8,r16 ;; |
||
451 | st8 [r16] = r42;; |
||
452 | add r16 = 8,r16 ;; |
||
453 | st8 [r16] = r43;; |
||
454 | add r16 = 8,r16 ;; |
||
455 | st8 [r16] = r44;; |
||
456 | add r16 = 8,r16 ;; |
||
457 | st8 [r16] = r45;; |
||
458 | add r16 = 8,r16 ;; |
||
459 | st8 [r16] = r46;; |
||
460 | add r16 = 8,r16 ;; |
||
461 | st8 [r16] = r47;; |
||
462 | add r16 = 8,r16 ;; |
||
463 | st8 [r16] = r48;; |
||
464 | add r16 = 8,r16 ;; |
||
465 | st8 [r16] = r49;; |
||
466 | add r16 = 8,r16 ;; |
||
467 | st8 [r16] = r50;; |
||
468 | add r16 = 8,r16 ;; |
||
469 | st8 [r16] = r51;; |
||
470 | add r16 = 8,r16 ;; |
||
471 | st8 [r16] = r52;; |
||
472 | add r16 = 8,r16 ;; |
||
473 | st8 [r16] = r53;; |
||
474 | add r16 = 8,r16 ;; |
||
475 | st8 [r16] = r54;; |
||
476 | add r16 = 8,r16 ;; |
||
477 | st8 [r16] = r55;; |
||
478 | add r16 = 8,r16 ;; |
||
479 | st8 [r16] = r56;; |
||
480 | add r16 = 8,r16 ;; |
||
481 | st8 [r16] = r57;; |
||
482 | add r16 = 8,r16 ;; |
||
483 | st8 [r16] = r58;; |
||
484 | add r16 = 8,r16 ;; |
||
485 | st8 [r16] = r59;; |
||
486 | add r16 = 8,r16 ;; |
||
487 | st8 [r16] = r60;; |
||
488 | add r16 = 8,r16 ;; |
||
489 | st8 [r16] = r61;; |
||
490 | add r16 = 8,r16 ;; |
||
491 | st8 [r16] = r62;; |
||
492 | add r16 = 8,r16 ;; |
||
493 | st8 [r16] = r63;; |
||
494 | add r16 = 8,r16 ;; |
||
495 | |||
496 | |||
497 | |||
498 | st8 [r16] = r64;; |
||
499 | add r16 = 8,r16 ;; |
||
500 | st8 [r16] = r65;; |
||
501 | add r16 = 8,r16 ;; |
||
502 | st8 [r16] = r66;; |
||
503 | add r16 = 8,r16 ;; |
||
504 | st8 [r16] = r67;; |
||
505 | add r16 = 8,r16 ;; |
||
506 | st8 [r16] = r68;; |
||
507 | add r16 = 8,r16 ;; |
||
508 | st8 [r16] = r69;; |
||
509 | add r16 = 8,r16 ;; |
||
510 | st8 [r16] = r70;; |
||
511 | add r16 = 8,r16 ;; |
||
512 | st8 [r16] = r71;; |
||
513 | add r16 = 8,r16 ;; |
||
514 | st8 [r16] = r72;; |
||
515 | add r16 = 8,r16 ;; |
||
516 | st8 [r16] = r73;; |
||
517 | add r16 = 8,r16 ;; |
||
518 | st8 [r16] = r74;; |
||
519 | add r16 = 8,r16 ;; |
||
520 | st8 [r16] = r75;; |
||
521 | add r16 = 8,r16 ;; |
||
522 | st8 [r16] = r76;; |
||
523 | add r16 = 8,r16 ;; |
||
524 | st8 [r16] = r77;; |
||
525 | add r16 = 8,r16 ;; |
||
526 | st8 [r16] = r78;; |
||
527 | add r16 = 8,r16 ;; |
||
528 | st8 [r16] = r79;; |
||
529 | add r16 = 8,r16 ;; |
||
530 | st8 [r16] = r80;; |
||
531 | add r16 = 8,r16 ;; |
||
532 | st8 [r16] = r81;; |
||
533 | add r16 = 8,r16 ;; |
||
534 | st8 [r16] = r82;; |
||
535 | add r16 = 8,r16 ;; |
||
536 | st8 [r16] = r83;; |
||
537 | add r16 = 8,r16 ;; |
||
538 | st8 [r16] = r84;; |
||
539 | add r16 = 8,r16 ;; |
||
540 | st8 [r16] = r85;; |
||
541 | add r16 = 8,r16 ;; |
||
542 | st8 [r16] = r86;; |
||
543 | add r16 = 8,r16 ;; |
||
544 | st8 [r16] = r87;; |
||
545 | add r16 = 8,r16 ;; |
||
546 | st8 [r16] = r88;; |
||
547 | add r16 = 8,r16 ;; |
||
548 | st8 [r16] = r89;; |
||
549 | add r16 = 8,r16 ;; |
||
550 | st8 [r16] = r90;; |
||
551 | add r16 = 8,r16 ;; |
||
552 | st8 [r16] = r91;; |
||
553 | add r16 = 8,r16 ;; |
||
554 | st8 [r16] = r92;; |
||
555 | add r16 = 8,r16 ;; |
||
556 | st8 [r16] = r93;; |
||
557 | add r16 = 8,r16 ;; |
||
558 | st8 [r16] = r94;; |
||
559 | add r16 = 8,r16 ;; |
||
560 | st8 [r16] = r95;; |
||
561 | add r16 = 8,r16 ;; |
||
562 | |||
563 | |||
564 | |||
565 | st8 [r16] = r96;; |
||
566 | add r16 = 8,r16 ;; |
||
567 | st8 [r16] = r97;; |
||
568 | add r16 = 8,r16 ;; |
||
569 | st8 [r16] = r98;; |
||
570 | add r16 = 8,r16 ;; |
||
571 | st8 [r16] = r99;; |
||
572 | add r16 = 8,r16 ;; |
||
573 | st8 [r16] = r100;; |
||
574 | add r16 = 8,r16 ;; |
||
575 | st8 [r16] = r101;; |
||
576 | add r16 = 8,r16 ;; |
||
577 | st8 [r16] = r102;; |
||
578 | add r16 = 8,r16 ;; |
||
579 | st8 [r16] = r103;; |
||
580 | add r16 = 8,r16 ;; |
||
581 | st8 [r16] = r104;; |
||
582 | add r16 = 8,r16 ;; |
||
583 | st8 [r16] = r105;; |
||
584 | add r16 = 8,r16 ;; |
||
585 | st8 [r16] = r106;; |
||
586 | add r16 = 8,r16 ;; |
||
587 | st8 [r16] = r107;; |
||
588 | add r16 = 8,r16 ;; |
||
589 | st8 [r16] = r108;; |
||
590 | add r16 = 8,r16 ;; |
||
591 | st8 [r16] = r109;; |
||
592 | add r16 = 8,r16 ;; |
||
593 | st8 [r16] = r110;; |
||
594 | add r16 = 8,r16 ;; |
||
595 | st8 [r16] = r111;; |
||
596 | add r16 = 8,r16 ;; |
||
597 | st8 [r16] = r112;; |
||
598 | add r16 = 8,r16 ;; |
||
599 | st8 [r16] = r113;; |
||
600 | add r16 = 8,r16 ;; |
||
601 | st8 [r16] = r114;; |
||
602 | add r16 = 8,r16 ;; |
||
603 | st8 [r16] = r115;; |
||
604 | add r16 = 8,r16 ;; |
||
605 | st8 [r16] = r116;; |
||
606 | add r16 = 8,r16 ;; |
||
607 | st8 [r16] = r117;; |
||
608 | add r16 = 8,r16 ;; |
||
609 | st8 [r16] = r118;; |
||
610 | add r16 = 8,r16 ;; |
||
611 | st8 [r16] = r119;; |
||
612 | add r16 = 8,r16 ;; |
||
613 | st8 [r16] = r120;; |
||
614 | add r16 = 8,r16 ;; |
||
615 | st8 [r16] = r121;; |
||
616 | add r16 = 8,r16 ;; |
||
617 | st8 [r16] = r122;; |
||
618 | add r16 = 8,r16 ;; |
||
619 | st8 [r16] = r123;; |
||
620 | add r16 = 8,r16 ;; |
||
621 | st8 [r16] = r124;; |
||
622 | add r16 = 8,r16 ;; |
||
623 | st8 [r16] = r125;; |
||
624 | add r16 = 8,r16 ;; |
||
625 | st8 [r16] = r126;; |
||
626 | add r16 = 8,r16 ;; |
||
627 | st8 [r16] = r127;; |
||
628 | add r16 = 8,r16 ;; |
||
629 | |||
630 | |||
631 | |||
632 | br.ret.sptk.many b0;; |
||
633 | |||
634 | |||
635 | |||
636 | |||
637 | |||
212 | vana | 638 | .macro Handler o h |
639 | .org IVT + \o |
||
640 | br \h;; |
||
641 | .endm |
||
642 | |||
220 | vana | 643 | .macro Handler2 o |
644 | .org IVT + \o |
||
238 | vana | 645 | br.call.sptk.many b0 = dump_gregs;; |
646 | mov r16 = \o ;; |
||
647 | bsw.1;; |
||
220 | vana | 648 | br universal_handler;; |
649 | .endm |
||
212 | vana | 650 | |
651 | |||
220 | vana | 652 | |
212 | vana | 653 | .global IVT |
654 | .align 32768 |
||
655 | IVT: |
||
656 | |||
220 | vana | 657 | |
658 | Handler2 0x0000 |
||
659 | Handler2 0x0400 |
||
660 | Handler2 0x0800 |
||
661 | Handler2 0x0c00 |
||
662 | Handler2 0x1000 |
||
663 | Handler2 0x1400 |
||
664 | Handler2 0x1800 |
||
665 | Handler2 0x1c00 |
||
666 | Handler2 0x2000 |
||
667 | Handler2 0x2400 |
||
668 | Handler2 0x2800 |
||
212 | vana | 669 | Handler 0x2c00 break_instruction |
435 | jermar | 670 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
220 | vana | 671 | Handler2 0x3400 |
672 | Handler2 0x3800 |
||
673 | Handler2 0x3c00 |
||
674 | Handler2 0x4000 |
||
675 | Handler2 0x4400 |
||
676 | Handler2 0x4800 |
||
677 | Handler2 0x4c00 |
||
678 | |||
679 | Handler2 0x5000 |
||
680 | Handler2 0x5100 |
||
681 | Handler2 0x5200 |
||
682 | Handler2 0x5300 |
||
238 | vana | 683 | #Handler 0x5400 general_exception |
684 | Handler2 0x5400 |
||
220 | vana | 685 | Handler2 0x5500 |
686 | Handler2 0x5600 |
||
687 | Handler2 0x5700 |
||
688 | Handler2 0x5800 |
||
689 | Handler2 0x5900 |
||
690 | Handler2 0x5a00 |
||
691 | Handler2 0x5b00 |
||
692 | Handler2 0x5c00 |
||
693 | Handler2 0x5d00 |
||
694 | Handler2 0x5e00 |
||
695 | Handler2 0x5f00 |
||
212 | vana | 696 | |
220 | vana | 697 | Handler2 0x6000 |
698 | Handler2 0x6100 |
||
699 | Handler2 0x6200 |
||
700 | Handler2 0x6300 |
||
701 | Handler2 0x6400 |
||
702 | Handler2 0x6500 |
||
703 | Handler2 0x6600 |
||
704 | Handler2 0x6700 |
||
705 | Handler2 0x6800 |
||
706 | Handler2 0x6900 |
||
707 | Handler2 0x6a00 |
||
708 | Handler2 0x6b00 |
||
709 | Handler2 0x6c00 |
||
710 | Handler2 0x6d00 |
||
711 | Handler2 0x6e00 |
||
712 | Handler2 0x6f00 |
||
212 | vana | 713 | |
220 | vana | 714 | Handler2 0x7000 |
715 | Handler2 0x7100 |
||
716 | Handler2 0x7200 |
||
717 | Handler2 0x7300 |
||
718 | Handler2 0x7400 |
||
719 | Handler2 0x7500 |
||
720 | Handler2 0x7600 |
||
721 | Handler2 0x7700 |
||
722 | Handler2 0x7800 |
||
723 | Handler2 0x7900 |
||
724 | Handler2 0x7a00 |
||
725 | Handler2 0x7b00 |
||
726 | Handler2 0x7c00 |
||
727 | Handler2 0x7d00 |
||
728 | Handler2 0x7e00 |
||
729 | Handler2 0x7f00 |
||
212 | vana | 730 | |
731 | |||
220 | vana | 732 | |
733 | |||
734 | |||
735 | |||
736 | |||
737 | |||
212 | vana | 738 | .align 32768 |
238 | vana | 739 | .global REG_DUMP |
740 | |||
741 | REG_DUMP: |
||
742 | .space 128*8 |
||
743 |