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35 | jermar | 1 | /* |
747 | jermar | 2 | * Copyright (C) 2005 - 2006 Jakub Jermar |
3 | * Copyright (C) 2006 Jakub Vana |
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35 | jermar | 4 | * All rights reserved. |
5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * |
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10 | * - Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * - Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * - The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |||
30 | #ifndef __ia64_PAGE_H__ |
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31 | #define __ia64_PAGE_H__ |
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32 | |||
747 | jermar | 33 | #include <arch/mm/frame.h> |
34 | #include <genarch/mm/page_ht.h> |
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121 | jermar | 35 | #include <arch/types.h> |
747 | jermar | 36 | #include <typedefs.h> |
37 | #include <debug.h> |
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35 | jermar | 38 | |
39 | #define PAGE_SIZE FRAME_SIZE |
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715 | vana | 40 | #define PAGE_WIDTH FRAME_WIDTH |
35 | jermar | 41 | |
537 | jermar | 42 | #define KA2PA(x) ((__address) (x)) |
43 | #define PA2KA(x) ((__address) (x)) |
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35 | jermar | 44 | |
125 | jermar | 45 | #define GET_PTL0_ADDRESS_ARCH() ((pte_t *) 0) |
120 | jermar | 46 | #define SET_PTL0_ADDRESS_ARCH(ptl0) |
47 | |||
699 | jermar | 48 | /** Implementation of page hash table interface. */ |
748 | jermar | 49 | #define HT_ENTRIES_ARCH (VHPT_SIZE/sizeof(pte_t)) |
50 | #define HT_HASH_ARCH(page, asid) vhpt_hash((page), (asid)) |
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699 | jermar | 51 | #define HT_COMPARE_ARCH(page, asid, t) 0 |
52 | #define HT_SLOT_EMPTY_ARCH(t) 1 |
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746 | jermar | 53 | #define HT_INVALIDATE_SLOT_ARCH(t) |
699 | jermar | 54 | #define HT_GET_NEXT_ARCH(t) 0 |
55 | #define HT_SET_NEXT_ARCH(t, s) |
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56 | #define HT_SET_RECORD_ARCH(t, page, asid, frame, flags) |
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57 | |||
748 | jermar | 58 | #define VRN_SHIFT 61 |
59 | #define VRN_MASK (7LL << VRN_SHIFT) |
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60 | |||
747 | jermar | 61 | #define VRN_KERNEL 0 |
748 | jermar | 62 | #define VRN_WORK 1LL |
747 | jermar | 63 | #define REGION_REGISTERS 8 |
715 | vana | 64 | |
747 | jermar | 65 | #define VHPT_WIDTH 20 /* 1M */ |
66 | #define VHPT_SIZE (1<<VHPT_WIDTH) |
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715 | vana | 67 | |
747 | jermar | 68 | #define VHPT_BASE page_ht /* Must be aligned to VHPT_SIZE */ |
715 | vana | 69 | |
747 | jermar | 70 | struct vhpt_tag_info { |
71 | unsigned long long tag : 63; |
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72 | unsigned ti : 1; |
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73 | } __attribute__ ((packed)); |
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710 | vana | 74 | |
747 | jermar | 75 | union vhpt_tag { |
76 | struct vhpt_tag_info tag_info; |
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77 | unsigned tag_word; |
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710 | vana | 78 | }; |
79 | |||
747 | jermar | 80 | struct vhpt_entry_present { |
710 | vana | 81 | /* Word 0 */ |
747 | jermar | 82 | unsigned p : 1; |
83 | unsigned : 1; |
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84 | unsigned ma : 3; |
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85 | unsigned a : 1; |
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86 | unsigned d : 1; |
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87 | unsigned pl : 2; |
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88 | unsigned ar : 3; |
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89 | unsigned long long ppn : 38; |
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90 | unsigned : 2; |
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91 | unsigned ed : 1; |
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92 | unsigned ig1 : 11; |
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710 | vana | 93 | |
94 | /* Word 1 */ |
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747 | jermar | 95 | unsigned : 2; |
96 | unsigned ps : 6; |
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97 | unsigned key : 24; |
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98 | unsigned : 32; |
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710 | vana | 99 | |
100 | /* Word 2 */ |
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747 | jermar | 101 | union vhpt_tag tag; |
102 | |||
710 | vana | 103 | /* Word 3 */ |
747 | jermar | 104 | unsigned long long next : 64; /**< Collision chain next pointer. */ |
105 | } __attribute__ ((packed)); |
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710 | vana | 106 | |
747 | jermar | 107 | struct vhpt_entry_not_present { |
710 | vana | 108 | /* Word 0 */ |
747 | jermar | 109 | unsigned p : 1; |
110 | unsigned long long ig0 : 52; |
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111 | unsigned ig1 : 11; |
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710 | vana | 112 | |
113 | /* Word 1 */ |
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747 | jermar | 114 | unsigned : 2; |
115 | unsigned ps : 6; |
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116 | unsigned long long ig2 : 56; |
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710 | vana | 117 | |
747 | jermar | 118 | /* Word 2 */ |
119 | union vhpt_tag tag; |
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710 | vana | 120 | |
121 | /* Word 3 */ |
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747 | jermar | 122 | unsigned long long next : 64; /**< Collision chain next pointer. */ |
710 | vana | 123 | |
747 | jermar | 124 | } __attribute__ ((packed)); |
710 | vana | 125 | |
747 | jermar | 126 | typedef union vhpt_entry { |
127 | struct vhpt_entry_present present; |
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128 | struct vhpt_entry_not_present not_present; |
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129 | } vhpt_entry; |
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710 | vana | 130 | |
747 | jermar | 131 | struct region_register_map { |
132 | unsigned ve : 1; |
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133 | unsigned : 1; |
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134 | unsigned ps : 6; |
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135 | unsigned rid : 24; |
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136 | unsigned : 32; |
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137 | } __attribute__ ((packed)); |
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684 | jermar | 138 | |
747 | jermar | 139 | typedef union region_register { |
140 | struct region_register_map map; |
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141 | unsigned long long word; |
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142 | } region_register; |
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715 | vana | 143 | |
747 | jermar | 144 | struct pta_register_map { |
145 | unsigned ve : 1; |
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146 | unsigned : 1; |
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147 | unsigned size : 6; |
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148 | unsigned vf : 1; |
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149 | unsigned : 6; |
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150 | unsigned long long base : 49; |
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151 | } __attribute__ ((packed)); |
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152 | |||
153 | typedef union pta_register { |
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154 | struct pta_register_map map; |
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155 | __u64 word; |
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156 | } pta_register; |
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157 | |||
158 | /** Return Translation Hashed Entry Address. |
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159 | * |
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160 | * VRN bits are used to read RID (ASID) from one |
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161 | * of the eight region registers registers. |
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162 | * |
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163 | * @param va Virtual address including VRN bits. |
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164 | * |
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165 | * @return Address of the head of VHPT collision chain. |
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166 | */ |
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167 | static inline __u64 thash(__u64 va) |
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715 | vana | 168 | { |
747 | jermar | 169 | __u64 ret; |
715 | vana | 170 | |
747 | jermar | 171 | __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
715 | vana | 172 | |
747 | jermar | 173 | return ret; |
174 | } |
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175 | |||
176 | /** Return Translation Hashed Entry Tag. |
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177 | * |
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178 | * VRN bits are used to read RID (ASID) from one |
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179 | * of the eight region registers. |
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180 | * |
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181 | * @param va Virtual address including VRN bits. |
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182 | * |
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183 | * @return The unique tag for VPN and RID in the collision chain returned by thash(). |
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184 | */ |
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185 | static inline __u64 ttag(__u64 va) |
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715 | vana | 186 | { |
747 | jermar | 187 | __u64 ret; |
715 | vana | 188 | |
747 | jermar | 189 | __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
190 | |||
191 | return ret; |
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192 | } |
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193 | |||
194 | /** Read Region Register. |
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195 | * |
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196 | * @param i Region register index. |
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197 | * |
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198 | * @return Current contents of rr[i]. |
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199 | */ |
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200 | static inline __u64 rr_read(index_t i) |
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715 | vana | 201 | { |
747 | jermar | 202 | __u64 ret; |
203 | |||
748 | jermar | 204 | ASSERT(i < REGION_REGISTERS); |
747 | jermar | 205 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i)); |
206 | |||
207 | return ret; |
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208 | } |
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715 | vana | 209 | |
210 | |||
747 | jermar | 211 | /** Write Region Register. |
212 | * |
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213 | * @param i Region register index. |
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214 | * @param v Value to be written to rr[i]. |
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215 | */ |
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216 | static inline void rr_write(index_t i, __u64 v) |
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715 | vana | 217 | { |
748 | jermar | 218 | ASSERT(i < REGION_REGISTERS); |
747 | jermar | 219 | __asm__ volatile ("mov rr[%0] = %1\n" : : "r" (i), "r" (v)); |
220 | } |
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221 | |||
222 | /** Read Page Table Register. |
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223 | * |
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224 | * @return Current value stored in PTA. |
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225 | */ |
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226 | static inline __u64 pta_read(void) |
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227 | { |
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228 | __u64 ret; |
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229 | |||
230 | __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
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231 | |||
232 | return ret; |
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233 | } |
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715 | vana | 234 | |
747 | jermar | 235 | /** Write Page Table Register. |
236 | * |
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237 | * @param v New value to be stored in PTA. |
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238 | */ |
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239 | static inline void pta_write(__u64 v) |
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240 | { |
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241 | __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); |
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242 | } |
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715 | vana | 243 | |
747 | jermar | 244 | extern void page_arch_init(void); |
748 | jermar | 245 | extern pte_t *vhpt_hash(__address page, asid_t asid); |
747 | jermar | 246 | |
35 | jermar | 247 | #endif |