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35 | jermar | 1 | /* |
747 | jermar | 2 | * Copyright (C) 2005 - 2006 Jakub Jermar |
3 | * Copyright (C) 2006 Jakub Vana |
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35 | jermar | 4 | * All rights reserved. |
5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * |
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10 | * - Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * - Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * - The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |||
30 | #ifndef __ia64_PAGE_H__ |
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31 | #define __ia64_PAGE_H__ |
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32 | |||
33 | #define PAGE_SIZE FRAME_SIZE |
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715 | vana | 34 | #define PAGE_WIDTH FRAME_WIDTH |
35 | jermar | 35 | |
901 | jermar | 36 | /** Bit width of the TLB-locked portion of kernel address space. */ |
37 | #define KERNEL_PAGE_WIDTH 28 /* 256M */ |
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35 | jermar | 38 | |
756 | jermar | 39 | #define SET_PTL0_ADDRESS_ARCH(x) /**< To be removed as situation permits. */ |
120 | jermar | 40 | |
749 | jermar | 41 | #define PPN_SHIFT 12 |
42 | |||
748 | jermar | 43 | #define VRN_SHIFT 61 |
44 | #define VRN_MASK (7LL << VRN_SHIFT) |
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901 | jermar | 45 | #define VA2VRN(va) ((va)>>VRN_SHIFT) |
869 | vana | 46 | |
47 | #ifdef __ASM__ |
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48 | #define VRN_KERNEL 7 |
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49 | #else |
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50 | #define VRN_KERNEL 7LL |
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51 | #endif |
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52 | |||
747 | jermar | 53 | #define REGION_REGISTERS 8 |
715 | vana | 54 | |
869 | vana | 55 | #define KA2PA(x) ((__address) (x-(VRN_KERNEL<<VRN_SHIFT))) |
56 | #define PA2KA(x) ((__address) (x+(VRN_KERNEL<<VRN_SHIFT))) |
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57 | |||
747 | jermar | 58 | #define VHPT_WIDTH 20 /* 1M */ |
792 | jermar | 59 | #define VHPT_SIZE (1 << VHPT_WIDTH) |
60 | #define VHPT_BASE 0 /* Must be aligned to VHPT_SIZE */ |
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715 | vana | 61 | |
751 | jermar | 62 | #define PTA_BASE_SHIFT 15 |
63 | |||
749 | jermar | 64 | /** Memory Attributes. */ |
65 | #define MA_WRITEBACK 0x0 |
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66 | #define MA_UNCACHEABLE 0x4 |
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67 | |||
68 | /** Privilege Levels. Only the most and the least privileged ones are ever used. */ |
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69 | #define PL_KERNEL 0x0 |
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70 | #define PL_USER 0x3 |
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71 | |||
72 | /* Access Rigths. Only certain combinations are used by the kernel. */ |
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73 | #define AR_READ 0x0 |
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74 | #define AR_EXECUTE 0x1 |
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75 | #define AR_WRITE 0x2 |
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76 | |||
901 | jermar | 77 | #ifndef __ASM__ |
818 | vana | 78 | |
901 | jermar | 79 | #include <arch/mm/frame.h> |
80 | #include <arch/barrier.h> |
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81 | #include <genarch/mm/page_ht.h> |
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82 | #include <arch/mm/asid.h> |
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83 | #include <arch/types.h> |
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84 | #include <typedefs.h> |
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85 | #include <debug.h> |
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818 | vana | 86 | |
747 | jermar | 87 | struct vhpt_tag_info { |
88 | unsigned long long tag : 63; |
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89 | unsigned ti : 1; |
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90 | } __attribute__ ((packed)); |
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710 | vana | 91 | |
747 | jermar | 92 | union vhpt_tag { |
93 | struct vhpt_tag_info tag_info; |
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94 | unsigned tag_word; |
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710 | vana | 95 | }; |
96 | |||
747 | jermar | 97 | struct vhpt_entry_present { |
710 | vana | 98 | /* Word 0 */ |
747 | jermar | 99 | unsigned p : 1; |
100 | unsigned : 1; |
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101 | unsigned ma : 3; |
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102 | unsigned a : 1; |
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103 | unsigned d : 1; |
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104 | unsigned pl : 2; |
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105 | unsigned ar : 3; |
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106 | unsigned long long ppn : 38; |
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107 | unsigned : 2; |
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108 | unsigned ed : 1; |
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109 | unsigned ig1 : 11; |
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710 | vana | 110 | |
111 | /* Word 1 */ |
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747 | jermar | 112 | unsigned : 2; |
113 | unsigned ps : 6; |
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114 | unsigned key : 24; |
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115 | unsigned : 32; |
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710 | vana | 116 | |
117 | /* Word 2 */ |
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747 | jermar | 118 | union vhpt_tag tag; |
119 | |||
710 | vana | 120 | /* Word 3 */ |
792 | jermar | 121 | __u64 ig3 : 64; |
747 | jermar | 122 | } __attribute__ ((packed)); |
710 | vana | 123 | |
747 | jermar | 124 | struct vhpt_entry_not_present { |
710 | vana | 125 | /* Word 0 */ |
747 | jermar | 126 | unsigned p : 1; |
127 | unsigned long long ig0 : 52; |
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128 | unsigned ig1 : 11; |
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710 | vana | 129 | |
130 | /* Word 1 */ |
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747 | jermar | 131 | unsigned : 2; |
132 | unsigned ps : 6; |
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133 | unsigned long long ig2 : 56; |
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710 | vana | 134 | |
747 | jermar | 135 | /* Word 2 */ |
136 | union vhpt_tag tag; |
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710 | vana | 137 | |
138 | /* Word 3 */ |
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792 | jermar | 139 | __u64 ig3 : 64; |
747 | jermar | 140 | } __attribute__ ((packed)); |
710 | vana | 141 | |
747 | jermar | 142 | typedef union vhpt_entry { |
143 | struct vhpt_entry_present present; |
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144 | struct vhpt_entry_not_present not_present; |
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749 | jermar | 145 | __u64 word[4]; |
792 | jermar | 146 | } vhpt_entry_t; |
710 | vana | 147 | |
747 | jermar | 148 | struct region_register_map { |
149 | unsigned ve : 1; |
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150 | unsigned : 1; |
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151 | unsigned ps : 6; |
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152 | unsigned rid : 24; |
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153 | unsigned : 32; |
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154 | } __attribute__ ((packed)); |
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684 | jermar | 155 | |
747 | jermar | 156 | typedef union region_register { |
157 | struct region_register_map map; |
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158 | unsigned long long word; |
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159 | } region_register; |
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715 | vana | 160 | |
747 | jermar | 161 | struct pta_register_map { |
162 | unsigned ve : 1; |
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163 | unsigned : 1; |
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164 | unsigned size : 6; |
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165 | unsigned vf : 1; |
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166 | unsigned : 6; |
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167 | unsigned long long base : 49; |
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168 | } __attribute__ ((packed)); |
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169 | |||
170 | typedef union pta_register { |
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171 | struct pta_register_map map; |
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172 | __u64 word; |
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173 | } pta_register; |
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174 | |||
175 | /** Return Translation Hashed Entry Address. |
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176 | * |
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177 | * VRN bits are used to read RID (ASID) from one |
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178 | * of the eight region registers registers. |
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179 | * |
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180 | * @param va Virtual address including VRN bits. |
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181 | * |
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182 | * @return Address of the head of VHPT collision chain. |
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183 | */ |
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184 | static inline __u64 thash(__u64 va) |
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715 | vana | 185 | { |
747 | jermar | 186 | __u64 ret; |
715 | vana | 187 | |
747 | jermar | 188 | __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
715 | vana | 189 | |
747 | jermar | 190 | return ret; |
191 | } |
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192 | |||
193 | /** Return Translation Hashed Entry Tag. |
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194 | * |
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195 | * VRN bits are used to read RID (ASID) from one |
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196 | * of the eight region registers. |
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197 | * |
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198 | * @param va Virtual address including VRN bits. |
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199 | * |
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200 | * @return The unique tag for VPN and RID in the collision chain returned by thash(). |
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201 | */ |
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202 | static inline __u64 ttag(__u64 va) |
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715 | vana | 203 | { |
747 | jermar | 204 | __u64 ret; |
715 | vana | 205 | |
747 | jermar | 206 | __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
207 | |||
208 | return ret; |
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209 | } |
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210 | |||
211 | /** Read Region Register. |
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212 | * |
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213 | * @param i Region register index. |
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214 | * |
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215 | * @return Current contents of rr[i]. |
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216 | */ |
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217 | static inline __u64 rr_read(index_t i) |
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715 | vana | 218 | { |
747 | jermar | 219 | __u64 ret; |
748 | jermar | 220 | ASSERT(i < REGION_REGISTERS); |
901 | jermar | 221 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); |
747 | jermar | 222 | return ret; |
223 | } |
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715 | vana | 224 | |
747 | jermar | 225 | /** Write Region Register. |
226 | * |
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227 | * @param i Region register index. |
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228 | * @param v Value to be written to rr[i]. |
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229 | */ |
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230 | static inline void rr_write(index_t i, __u64 v) |
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715 | vana | 231 | { |
748 | jermar | 232 | ASSERT(i < REGION_REGISTERS); |
818 | vana | 233 | __asm__ volatile ( |
901 | jermar | 234 | "mov rr[%0] = %1\n" |
235 | : |
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236 | : "r" (i << VRN_SHIFT), "r" (v) |
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237 | ); |
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747 | jermar | 238 | } |
239 | |||
240 | /** Read Page Table Register. |
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241 | * |
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242 | * @return Current value stored in PTA. |
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243 | */ |
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244 | static inline __u64 pta_read(void) |
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245 | { |
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246 | __u64 ret; |
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247 | |||
248 | __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
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249 | |||
250 | return ret; |
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251 | } |
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715 | vana | 252 | |
747 | jermar | 253 | /** Write Page Table Register. |
254 | * |
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255 | * @param v New value to be stored in PTA. |
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256 | */ |
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257 | static inline void pta_write(__u64 v) |
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258 | { |
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259 | __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); |
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260 | } |
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715 | vana | 261 | |
747 | jermar | 262 | extern void page_arch_init(void); |
263 | |||
792 | jermar | 264 | extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid); |
265 | extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v); |
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266 | extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags); |
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267 | |||
35 | jermar | 268 | #endif |
869 | vana | 269 | |
270 | #endif |