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173 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
173 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup ia64   
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 * @{
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 */
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/** @file
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 */
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#ifndef KERN_ia64_ASM_H_
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#define KERN_ia64_ASM_H_
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#include <config.h>
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#include <arch/types.h>
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#include <arch/register.h>
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2726 vana 43
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
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static inline void  outb(uint64_t port,uint8_t v)
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{
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    *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
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2515 vana 49
    asm volatile ("mf\n" ::: "memory");
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}
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static inline uint8_t inb(uint64_t port)
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{
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    asm volatile ("mf\n" ::: "memory");
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2515 vana 57
    return *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
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}
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/** Return base address of current stack
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 *
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE long.
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 * The stack must start on page boundary.
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 */
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static inline uintptr_t get_stack_base(void)
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{
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    uint64_t v;
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2082 decky 72
    asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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74
    return v;
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}
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/** Return Processor State Register.
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 *
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 * @return PSR.
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 */
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static inline uint64_t psr_read(void)
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{
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    uint64_t v;
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2082 decky 85
    asm volatile ("mov %0 = psr\n" : "=r" (v));
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87
    return v;
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}
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/** Read IVA (Interruption Vector Address).
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 *
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 * @return Return location of interruption vector table.
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 */
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static inline uint64_t iva_read(void)
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{
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    uint64_t v;
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2082 decky 98
    asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
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100
    return v;
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}
102
 
103
/** Write IVA (Interruption Vector Address) register.
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 *
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 * @param v New location of interruption vector table.
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 */
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static inline void iva_write(uint64_t v)
470 jermar 108
{
2082 decky 109
    asm volatile ("mov cr.iva = %0\n" : : "r" (v));
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}
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112
 
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/** Read IVR (External Interrupt Vector Register).
431 jermar 114
 *
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 * @return Highest priority, pending, unmasked external interrupt vector.
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 */
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static inline uint64_t ivr_read(void)
431 jermar 118
{
1780 jermar 119
    uint64_t v;
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2082 decky 121
    asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
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    return v;
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}
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/** Write ITC (Interval Timer Counter) register.
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 *
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 * @param v New counter value.
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 */
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static inline void itc_write(uint64_t v)
432 jermar 131
{
2082 decky 132
    asm volatile ("mov ar.itc = %0\n" : : "r" (v));
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}
431 jermar 134
 
432 jermar 135
/** Read ITC (Interval Timer Counter) register.
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 *
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 * @return Current counter value.
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 */
1780 jermar 139
static inline uint64_t itc_read(void)
432 jermar 140
{
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    uint64_t v;
432 jermar 142
 
2082 decky 143
    asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
432 jermar 144
 
145
    return v;
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}
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/** Write ITM (Interval Timer Match) register.
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 *
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 * @param v New match value.
432 jermar 151
 */
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static inline void itm_write(uint64_t v)
432 jermar 153
{
2082 decky 154
    asm volatile ("mov cr.itm = %0\n" : : "r" (v));
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}
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1488 vana 157
/** Read ITM (Interval Timer Match) register.
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 *
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 * @return Match value.
160
 */
1780 jermar 161
static inline uint64_t itm_read(void)
1488 vana 162
{
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    uint64_t v;
1488 vana 164
 
2082 decky 165
    asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
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167
    return v;
168
}
169
 
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/** Read ITV (Interval Timer Vector) register.
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 *
172
 * @return Current vector and mask bit.
173
 */
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static inline uint64_t itv_read(void)
433 jermar 175
{
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    uint64_t v;
433 jermar 177
 
2082 decky 178
    asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
433 jermar 179
 
180
    return v;
181
}
182
 
432 jermar 183
/** Write ITV (Interval Timer Vector) register.
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 *
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 * @param v New vector and mask bit.
432 jermar 186
 */
1780 jermar 187
static inline void itv_write(uint64_t v)
432 jermar 188
{
2082 decky 189
    asm volatile ("mov cr.itv = %0\n" : : "r" (v));
432 jermar 190
}
238 vana 191
 
432 jermar 192
/** Write EOI (End Of Interrupt) register.
193
 *
1708 jermar 194
 * @param v This value is ignored.
432 jermar 195
 */
1780 jermar 196
static inline void eoi_write(uint64_t v)
432 jermar 197
{
2082 decky 198
    asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
432 jermar 199
}
200
 
201
/** Read TPR (Task Priority Register).
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 *
203
 * @return Current value of TPR.
204
 */
1780 jermar 205
static inline uint64_t tpr_read(void)
432 jermar 206
{
1780 jermar 207
    uint64_t v;
432 jermar 208
 
2082 decky 209
    asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
432 jermar 210
 
211
    return v;
212
}
213
 
214
/** Write TPR (Task Priority Register).
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 *
1708 jermar 216
 * @param v New value of TPR.
432 jermar 217
 */
1780 jermar 218
static inline void tpr_write(uint64_t v)
432 jermar 219
{
2082 decky 220
    asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
432 jermar 221
}
222
 
223
/** Disable interrupts.
224
 *
225
 * Disable interrupts and return previous
226
 * value of PSR.
227
 *
228
 * @return Old interrupt priority level.
229
 */
230
static ipl_t interrupts_disable(void)
231
{
1780 jermar 232
    uint64_t v;
432 jermar 233
 
2082 decky 234
    asm volatile (
432 jermar 235
        "mov %0 = psr\n"
236
        "rsm %1\n"
237
        : "=r" (v)
238
        : "i" (PSR_I_MASK)
239
    );
240
 
241
    return (ipl_t) v;
242
}
243
 
244
/** Enable interrupts.
245
 *
246
 * Enable interrupts and return previous
247
 * value of PSR.
248
 *
249
 * @return Old interrupt priority level.
250
 */
251
static ipl_t interrupts_enable(void)
252
{
1780 jermar 253
    uint64_t v;
432 jermar 254
 
2082 decky 255
    asm volatile (
432 jermar 256
        "mov %0 = psr\n"
257
        "ssm %1\n"
258
        ";;\n"
259
        "srlz.d\n"
260
        : "=r" (v)
261
        : "i" (PSR_I_MASK)
262
    );
263
 
264
    return (ipl_t) v;
265
}
266
 
267
/** Restore interrupt priority level.
268
 *
269
 * Restore PSR.
270
 *
271
 * @param ipl Saved interrupt priority level.
272
 */
273
static inline void interrupts_restore(ipl_t ipl)
274
{
472 jermar 275
    if (ipl & PSR_I_MASK)
276
        (void) interrupts_enable();
277
    else
278
        (void) interrupts_disable();
432 jermar 279
}
280
 
281
/** Return interrupt priority level.
282
 *
283
 * @return PSR.
284
 */
285
static inline ipl_t interrupts_read(void)
286
{
919 jermar 287
    return (ipl_t) psr_read();
432 jermar 288
}
289
 
746 jermar 290
/** Disable protection key checking. */
291
static inline void pk_disable(void)
292
{
2082 decky 293
    asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
746 jermar 294
}
295
 
432 jermar 296
extern void cpu_halt(void);
297
extern void cpu_sleep(void);
1780 jermar 298
extern void asm_delay_loop(uint32_t t);
238 vana 299
 
1780 jermar 300
extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);
919 jermar 301
 
173 jermar 302
#endif
1702 cejka 303
 
1888 jermar 304
/** @}
1702 cejka 305
 */