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/*
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 * Copyright (c) 2007 Petr Stepan
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup arm32
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 * @{
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 */
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/** @file
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 *  @brief Exception handlers and exception initialization routines.
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 */
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#include <arch/exception.h>
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#include <arch/memstr.h>
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#include <arch/regutils.h>
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#include <interrupt.h>
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#include <arch/mm/page_fault.h>
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#include <arch/barrier.h>
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#include <print.h>
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#include <syscall/syscall.h>
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#include <udebug/udebug.h>
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#ifdef MACHINE_testarm
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    #include <arch/mach/testarm/testarm.h>
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#endif
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#ifdef MACHINE_integratorcp
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    #include <arch/mach/integratorcp/integratorcp.h>
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#endif
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/** Offset used in calculation of exception handler's relative address.
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 *
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 * @see install_handler()
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 */
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#define PREFETCH_OFFSET      0x8
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/** LDR instruction's code */
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#define LDR_OPCODE           0xe59ff000
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/** Number of exception vectors. */
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#define EXC_VECTORS          8
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/** Size of memory block occupied by exception vectors. */
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#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
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/** Updates specified exception vector to jump to given handler.
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 *
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 *  Addresses of handlers are stored in memory following exception vectors.
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 */
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static void install_handler(unsigned handler_addr, unsigned *vector)
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{
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    /* relative address (related to exc. vector) of the word
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     * where handler's address is stored
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    */
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    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
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        PREFETCH_OFFSET;
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    /* make it LDR instruction and store at exception vector */
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    *vector = handler_address_ptr | LDR_OPCODE;
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    smc_coherence(*vector);
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    /* store handler's address */
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    *(vector + EXC_VECTORS) = handler_addr;
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}
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/** Software Interrupt handler.
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 *
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 * Dispatches the syscall.
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 */
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static void swi_exception(int exc_no, istate_t *istate)
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{
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    istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
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        istate->r3, istate->r4, istate->r5, istate->r6);
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}
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/** Fills exception vectors with appropriate exception handlers. */
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void install_exception_handlers(void)
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{
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    install_handler((unsigned) reset_exception_entry,
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        (unsigned *) EXC_RESET_VEC);
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    install_handler((unsigned) undef_instr_exception_entry,
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        (unsigned *) EXC_UNDEF_INSTR_VEC);
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    install_handler((unsigned) swi_exception_entry,
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        (unsigned *) EXC_SWI_VEC);
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    install_handler((unsigned) prefetch_abort_exception_entry,
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        (unsigned *) EXC_PREFETCH_ABORT_VEC);
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    install_handler((unsigned) data_abort_exception_entry,
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        (unsigned *) EXC_DATA_ABORT_VEC);
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    install_handler((unsigned) irq_exception_entry,
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        (unsigned *) EXC_IRQ_VEC);
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    install_handler((unsigned) fiq_exception_entry,
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        (unsigned *) EXC_FIQ_VEC);
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}
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#ifdef HIGH_EXCEPTION_VECTORS
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/** Activates use of high exception vectors addresses. */
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static void high_vectors(void)
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{
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    uint32_t control_reg;
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    asm volatile (
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        "mrc p15, 0, %[control_reg], c1, c1"
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        : [control_reg] "=r" (control_reg)
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    );
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    /* switch on the high vectors bit */
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    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
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    asm volatile (
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        "mcr p15, 0, %[control_reg], c1, c1"
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        :: [control_reg] "r" (control_reg)
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    );
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}
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#endif
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/** Interrupt Exception handler.
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 *
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 * Determines the sources of interrupt and calls their handlers.
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 */
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static void irq_exception(int exc_no, istate_t *istate)
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{
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    machine_irq_exception(exc_no, istate);
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}
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/** Initializes exception handling.
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 *
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 * Installs low-level exception handlers and then registers
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 * exceptions and their handlers to kernel exception dispatcher.
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 */
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void exception_init(void)
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{
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#ifdef HIGH_EXCEPTION_VECTORS
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    high_vectors();
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#endif
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    install_exception_handlers();
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    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
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    exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
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        (iroutine) prefetch_abort);
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    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
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    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
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}
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/** Prints #istate_t structure content.
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 *
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 * @param istate Structure to be printed.
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 */
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void print_istate(istate_t *istate)
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{
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    printf("istate dump:\n");
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    printf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
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        istate->r0, istate->r1, istate->r2, istate->r3);
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    printf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
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        istate->r4, istate->r5, istate->r6, istate->r7);
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    printf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
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        istate->r8, istate->r9, istate->r10, istate->r11);
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    printf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
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        istate->r12, istate->sp, istate->lr, istate->spsr);
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    printf(" pc: %x\n", istate->pc);
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}
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/** @}
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 */