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2128 | jermar | 1 | /* |
2465 | jermar | 2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2128 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32mm |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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2465 | jermar | 33 | * @brief Paging related declarations. |
2128 | jermar | 34 | */ |
35 | |||
36 | #ifndef KERN_arm32_PAGE_H_ |
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37 | #define KERN_arm32_PAGE_H_ |
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38 | |||
39 | #include <arch/mm/frame.h> |
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2465 | jermar | 40 | #include <mm/mm.h> |
41 | #include <arch/exception.h> |
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2128 | jermar | 42 | |
43 | #define PAGE_WIDTH FRAME_WIDTH |
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44 | #define PAGE_SIZE FRAME_SIZE |
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45 | |||
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
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47 | |||
48 | #ifndef __ASM__ |
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49 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
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50 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
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51 | #else |
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52 | # define KA2PA(x) ((x) - 0x80000000) |
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53 | # define PA2KA(x) ((x) + 0x80000000) |
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54 | #endif |
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55 | |||
56 | #ifdef KERNEL |
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57 | |||
2467 | jermar | 58 | /* Number of entries in each level. */ |
2465 | jermar | 59 | #define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ |
60 | #define PTL1_ENTRIES_ARCH 0 |
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61 | #define PTL2_ENTRIES_ARCH 0 |
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62 | /* coarse page tables used (256 * 4 = 1KB per page) */ |
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63 | #define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ |
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2128 | jermar | 64 | |
2467 | jermar | 65 | /* Page table sizes for each level. */ |
2465 | jermar | 66 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
67 | #define PTL1_SIZE_ARCH 0 |
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68 | #define PTL2_SIZE_ARCH 0 |
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69 | #define PTL3_SIZE_ARCH ONE_FRAME |
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2128 | jermar | 70 | |
2467 | jermar | 71 | /* Macros calculating indices into page tables for each level. */ |
2465 | jermar | 72 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
73 | #define PTL1_INDEX_ARCH(vaddr) 0 |
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74 | #define PTL2_INDEX_ARCH(vaddr) 0 |
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75 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
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2128 | jermar | 76 | |
2467 | jermar | 77 | /* Get PTE address accessors for each level. */ |
2465 | jermar | 78 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
79 | ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) |
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80 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
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81 | (ptl1) |
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82 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
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83 | (ptl2) |
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84 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
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85 | ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) |
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2128 | jermar | 86 | |
2467 | jermar | 87 | /* Set PTE address accessors for each level. */ |
2465 | jermar | 88 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
89 | (set_ptl0_addr((pte_level0_t *) (ptl0))) |
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90 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
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91 | (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) |
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92 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
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93 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
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94 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
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95 | (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) |
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2128 | jermar | 96 | |
2467 | jermar | 97 | /* Get PTE flags accessors for each level. */ |
2465 | jermar | 98 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
99 | get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) |
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100 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
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101 | PAGE_PRESENT |
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102 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
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103 | PAGE_PRESENT |
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104 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
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105 | get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) |
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2128 | jermar | 106 | |
2467 | jermar | 107 | /* Set PTE flags accessors for each level. */ |
2465 | jermar | 108 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
109 | set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) |
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110 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
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111 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
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112 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
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113 | set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) |
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2128 | jermar | 114 | |
2467 | jermar | 115 | /* Macros for querying the last-level PTE entries. */ |
2465 | jermar | 116 | #define PTE_VALID_ARCH(pte) \ |
117 | (*((uint32_t *) (pte)) != 0) |
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118 | #define PTE_PRESENT_ARCH(pte) \ |
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119 | (((pte_level0_t *) (pte))->descriptor_type != 0) |
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120 | #define PTE_GET_FRAME_ARCH(pte) \ |
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121 | (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) |
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122 | #define PTE_WRITABLE_ARCH(pte) \ |
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123 | (((pte_level1_t *) (pte))->access_permission_0 == \ |
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124 | PTE_AP_USER_RW_KERNEL_RW) |
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125 | #define PTE_EXECUTABLE_ARCH(pte) \ |
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126 | 1 |
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127 | |||
2128 | jermar | 128 | #ifndef __ASM__ |
129 | |||
2465 | jermar | 130 | /** Level 0 page table entry. */ |
131 | typedef struct { |
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132 | /* 0b01 for coarse tables, see below for details */ |
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2467 | jermar | 133 | unsigned descriptor_type : 2; |
134 | unsigned impl_specific : 3; |
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135 | unsigned domain : 4; |
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136 | unsigned should_be_zero : 1; |
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2128 | jermar | 137 | |
2465 | jermar | 138 | /* Pointer to the coarse 2nd level page table (holding entries for small |
139 | * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page |
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140 | * tables that may hold even tiny pages (1KB) but they are bigger (4KB |
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141 | * per table in comparison with 1KB per the coarse table) |
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142 | */ |
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2467 | jermar | 143 | unsigned coarse_table_addr : 22; |
2465 | jermar | 144 | } ATTRIBUTE_PACKED pte_level0_t; |
145 | |||
146 | /** Level 1 page table entry (small (4KB) pages used). */ |
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147 | typedef struct { |
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148 | |||
149 | /* 0b10 for small pages */ |
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2467 | jermar | 150 | unsigned descriptor_type : 2; |
151 | unsigned bufferable : 1; |
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152 | unsigned cacheable : 1; |
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2465 | jermar | 153 | |
154 | /* access permissions for each of 4 subparts of a page |
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155 | * (for each 1KB when small pages used */ |
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156 | unsigned access_permission_0 : 2; |
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157 | unsigned access_permission_1 : 2; |
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158 | unsigned access_permission_2 : 2; |
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159 | unsigned access_permission_3 : 2; |
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2467 | jermar | 160 | unsigned frame_base_addr : 20; |
2465 | jermar | 161 | } ATTRIBUTE_PACKED pte_level1_t; |
162 | |||
163 | |||
164 | /* Level 1 page tables access permissions */ |
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165 | |||
166 | /** User mode: no access, privileged mode: no access. */ |
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167 | #define PTE_AP_USER_NO_KERNEL_NO 0 |
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168 | |||
169 | /** User mode: no access, privileged mode: read/write. */ |
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170 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
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171 | |||
172 | /** User mode: read only, privileged mode: read/write. */ |
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173 | #define PTE_AP_USER_RO_KERNEL_RW 2 |
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174 | |||
175 | /** User mode: read/write, privileged mode: read/write. */ |
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176 | #define PTE_AP_USER_RW_KERNEL_RW 3 |
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177 | |||
178 | |||
179 | /* pte_level0_t and pte_level1_t descriptor_type flags */ |
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180 | |||
181 | /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
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182 | #define PTE_DESCRIPTOR_NOT_PRESENT 0 |
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183 | |||
184 | /** pte_level0_t coarse page table flag (used in descriptor_type). */ |
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185 | #define PTE_DESCRIPTOR_COARSE_TABLE 1 |
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186 | |||
187 | /** pte_level1_t small page table flag (used in descriptor type). */ |
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188 | #define PTE_DESCRIPTOR_SMALL_PAGE 2 |
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189 | |||
190 | |||
191 | /** Sets the address of level 0 page table. |
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192 | * |
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193 | * @param pt Pointer to the page table to set. |
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194 | */ |
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2467 | jermar | 195 | static inline void set_ptl0_addr(pte_level0_t *pt) |
2128 | jermar | 196 | { |
2465 | jermar | 197 | asm volatile ( |
198 | "mcr p15, 0, %0, c2, c0, 0 \n" |
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199 | : |
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200 | : "r"(pt) |
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201 | ); |
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2128 | jermar | 202 | } |
203 | |||
2465 | jermar | 204 | |
205 | /** Returns level 0 page table entry flags. |
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206 | * |
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207 | * @param pt Level 0 page table. |
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208 | * @param i Index of the entry to return. |
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209 | */ |
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210 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
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2128 | jermar | 211 | { |
2465 | jermar | 212 | pte_level0_t *p = &pt[i]; |
213 | int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); |
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214 | |||
215 | return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | |
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216 | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | |
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217 | (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); |
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2128 | jermar | 218 | } |
219 | |||
2465 | jermar | 220 | /** Returns level 1 page table entry flags. |
221 | * |
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222 | * @param pt Level 1 page table. |
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223 | * @param i Index of the entry to return. |
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224 | */ |
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225 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
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226 | { |
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227 | pte_level1_t *p = &pt[i]; |
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228 | |||
229 | int dt = p->descriptor_type; |
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230 | int ap = p->access_permission_0; |
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231 | |||
232 | return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
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233 | ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | |
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234 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | |
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235 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
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236 | ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | |
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237 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | |
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238 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
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239 | (1 << PAGE_EXEC_SHIFT) | |
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240 | (p->bufferable << PAGE_CACHEABLE); |
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241 | } |
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242 | |||
243 | |||
244 | /** Sets flags of level 0 page table entry. |
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245 | * |
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246 | * @param pt level 0 page table |
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247 | * @param i index of the entry to be changed |
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248 | * @param flags new flags |
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249 | */ |
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250 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
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251 | { |
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252 | pte_level0_t *p = &pt[i]; |
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253 | |||
254 | if (flags & PAGE_NOT_PRESENT) { |
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255 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
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256 | /* |
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257 | * Ensures that the entry will be recognized as valid when |
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258 | * PTE_VALID_ARCH applied. |
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259 | */ |
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260 | p->should_be_zero = 1; |
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261 | } else { |
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262 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
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263 | p->should_be_zero = 0; |
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264 | } |
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265 | } |
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266 | |||
267 | |||
268 | /** Sets flags of level 1 page table entry. |
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269 | * |
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270 | * We use same access rights for the whole page. When page is not preset we |
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271 | * store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct |
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272 | * page entry, see #PAGE_VALID_ARCH). |
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273 | * |
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274 | * @param pt Level 1 page table. |
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275 | * @param i Index of the entry to be changed. |
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276 | * @param flags New flags. |
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277 | */ |
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278 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
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279 | { |
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280 | pte_level1_t *p = &pt[i]; |
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281 | |||
282 | if (flags & PAGE_NOT_PRESENT) { |
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283 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
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284 | p->access_permission_3 = 1; |
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285 | } else { |
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286 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
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287 | p->access_permission_3 = p->access_permission_0; |
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288 | } |
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289 | |||
290 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
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291 | |||
292 | /* default access permission */ |
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293 | p->access_permission_0 = p->access_permission_1 = |
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294 | p->access_permission_2 = p->access_permission_3 = |
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295 | PTE_AP_USER_NO_KERNEL_RW; |
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296 | |||
297 | if (flags & PAGE_USER) { |
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298 | if (flags & PAGE_READ) { |
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299 | p->access_permission_0 = p->access_permission_1 = |
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300 | p->access_permission_2 = p->access_permission_3 = |
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301 | PTE_AP_USER_RO_KERNEL_RW; |
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302 | } |
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303 | if (flags & PAGE_WRITE) { |
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304 | p->access_permission_0 = p->access_permission_1 = |
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305 | p->access_permission_2 = p->access_permission_3 = |
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306 | PTE_AP_USER_RW_KERNEL_RW; |
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307 | } |
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308 | } |
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309 | } |
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310 | |||
311 | |||
2128 | jermar | 312 | extern void page_arch_init(void); |
313 | |||
2465 | jermar | 314 | |
2128 | jermar | 315 | #endif /* __ASM__ */ |
316 | |||
317 | #endif /* KERNEL */ |
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318 | |||
319 | #endif |
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320 | |||
321 | /** @} |
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322 | */ |