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Rev | Author | Line No. | Line |
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1018 | decky | 1 | # |
2071 | jermar | 2 | # Copyright (c) 2006 Martin Decky |
1018 | decky | 3 | # All rights reserved. |
4 | # |
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5 | # Redistribution and use in source and binary forms, with or without |
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6 | # modification, are permitted provided that the following conditions |
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7 | # are met: |
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8 | # |
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9 | # - Redistributions of source code must retain the above copyright |
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10 | # notice, this list of conditions and the following disclaimer. |
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11 | # - Redistributions in binary form must reproduce the above copyright |
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12 | # notice, this list of conditions and the following disclaimer in the |
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13 | # documentation and/or other materials provided with the distribution. |
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14 | # - The name of the author may not be used to endorse or promote products |
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15 | # derived from this software without specific prior written permission. |
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16 | # |
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17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | # |
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28 | |||
29 | #include "regname.h" |
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4377 | svoboda | 30 | #include "main.h" |
1018 | decky | 31 | |
32 | .set noat |
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33 | .set noreorder |
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34 | .set nomacro |
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35 | |||
36 | .section BOOTSTRAP |
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37 | |||
38 | .global start |
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39 | start: |
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1685 | decky | 40 | |
4377 | svoboda | 41 | /* Setup CPU map (on msim this code |
42 | is executed in parallel on all CPUs, |
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43 | but it not an issue) */ |
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44 | la $a0, CPUMAP |
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45 | |||
46 | sw $zero, 0($a0) |
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47 | sw $zero, 4($a0) |
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48 | sw $zero, 8($a0) |
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49 | sw $zero, 12($a0) |
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50 | |||
51 | sw $zero, 16($a0) |
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52 | sw $zero, 20($a0) |
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53 | sw $zero, 24($a0) |
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54 | sw $zero, 28($a0) |
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55 | |||
56 | sw $zero, 32($a0) |
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57 | sw $zero, 36($a0) |
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58 | sw $zero, 40($a0) |
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59 | sw $zero, 44($a0) |
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60 | |||
61 | sw $zero, 48($a0) |
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62 | sw $zero, 52($a0) |
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63 | sw $zero, 56($a0) |
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64 | sw $zero, 60($a0) |
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65 | |||
66 | sw $zero, 64($a0) |
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67 | sw $zero, 68($a0) |
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68 | sw $zero, 72($a0) |
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69 | sw $zero, 76($a0) |
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70 | |||
71 | sw $zero, 80($a0) |
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72 | sw $zero, 84($a0) |
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73 | sw $zero, 88($a0) |
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74 | sw $zero, 92($a0) |
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75 | |||
76 | sw $zero, 96($a0) |
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77 | sw $zero, 100($a0) |
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78 | sw $zero, 104($a0) |
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79 | sw $zero, 108($a0) |
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80 | |||
81 | sw $zero, 112($a0) |
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82 | sw $zero, 116($a0) |
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83 | sw $zero, 120($a0) |
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84 | sw $zero, 124($a0) |
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85 | |||
86 | lui $a1, 1 |
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87 | |||
88 | #ifdef MACHINE_msim |
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89 | |||
90 | /* Read dorder value */ |
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91 | la $k0, MSIM_DORDER_ADDRESS |
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92 | lw $k1, ($k0) |
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93 | |||
94 | /* If we are not running on BSP |
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95 | then end in an infinite loop */ |
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96 | beq $k1, $zero, bsp |
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1018 | decky | 97 | nop |
4377 | svoboda | 98 | |
99 | /* Record CPU presence */ |
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100 | sll $a2, $k1, 2 |
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101 | addu $a2, $a2, $a0 |
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102 | sw $a1, ($a2) |
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103 | |||
104 | loop: |
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105 | j loop |
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106 | nop |
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107 | |||
108 | #endif |
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109 | |||
110 | bsp: |
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111 | /* Record CPU presence */ |
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112 | sw $a1, ($a0) |
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113 | |||
114 | /* Setup initial stack */ |
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115 | la $sp, INITIAL_STACK |
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116 | |||
117 | j bootstrap |
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118 | nop |