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3743 rimsky 1
#
2
# Copyright (c) 2005 Jakub Jermar
3
# Copyright (c) 2008 Pavel Rimsky
4
# All rights reserved.
5
#
6
# Redistribution and use in source and binary forms, with or without
7
# modification, are permitted provided that the following conditions
8
# are met:
9
#
10
# - Redistributions of source code must retain the above copyright
11
#   notice, this list of conditions and the following disclaimer.
12
# - Redistributions in binary form must reproduce the above copyright
13
#   notice, this list of conditions and the following disclaimer in the
14
#   documentation and/or other materials provided with the distribution.
15
# - The name of the author may not be used to endorse or promote products
16
#   derived from this software without specific prior written permission.
17
#
18
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
#
29
 
30
/**
31
 * @file
32
 * @brief This file contains kernel trap table.
33
 */
34
 
35
.register %g2, #scratch
36
.register %g3, #scratch
37
 
38
.text
39
 
40
#include <arch/trap/trap_table.h>
41
#include <arch/trap/regwin.h>
42
#include <arch/trap/interrupt.h>
43
#include <arch/trap/exception.h>
44
#include <arch/trap/syscall.h>
45
#include <arch/trap/sun4v/mmu.h>
46
#include <arch/mm/sun4v/mmu.h>
47
#include <arch/mm/page.h>
48
#include <arch/stack.h>
49
#include <arch/sun4v/regdef.h>
50
 
51
#define TABLE_SIZE	TRAP_TABLE_SIZE
52
#define ENTRY_SIZE	TRAP_TABLE_ENTRY_SIZE
53
 
54
/*
55
 * Kernel trap table.
56
 */
57
.align TABLE_SIZE
58
.global trap_table
59
trap_table:
60
 
61
/* TT = 0x08, TL = 0, instruction_access_exception */
62
.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
63
.global instruction_access_exception_tl0
64
instruction_access_exception_tl0:
65
	/*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
66
	PREEMPTIBLE_HANDLER instruction_access_exception*/
67
 
68
/* TT = 0x0a, TL = 0, instruction_access_error */
69
.org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE
70
.global instruction_access_error_tl0
71
instruction_access_error_tl0:
72
	PREEMPTIBLE_HANDLER instruction_access_error
73
 
74
/* TT = 0x10, TL = 0, illegal_instruction */
75
.org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
76
.global illegal_instruction_tl0
77
illegal_instruction_tl0:
78
	PREEMPTIBLE_HANDLER illegal_instruction
79
 
80
/* TT = 0x11, TL = 0, privileged_opcode */
81
.org trap_table + TT_PRIVILEGED_OPCODE*ENTRY_SIZE
82
.global privileged_opcode_tl0
83
privileged_opcode_tl0:
84
	PREEMPTIBLE_HANDLER privileged_opcode
85
 
86
/* TT = 0x12, TL = 0, unimplemented_LDD */
87
.org trap_table + TT_UNIMPLEMENTED_LDD*ENTRY_SIZE
88
.global unimplemented_LDD_tl0
89
unimplemented_LDD_tl0:
90
	PREEMPTIBLE_HANDLER unimplemented_LDD
91
 
92
/* TT = 0x13, TL = 0, unimplemented_STD */
93
.org trap_table + TT_UNIMPLEMENTED_STD*ENTRY_SIZE
94
.global unimplemented_STD_tl0
95
unimplemented_STD_tl0:
96
	PREEMPTIBLE_HANDLER unimplemented_STD
97
 
98
/* TT = 0x20, TL = 0, fb_disabled handler */
99
.org trap_table + TT_FP_DISABLED*ENTRY_SIZE
100
.global fb_disabled_tl0
101
fp_disabled_tl0:
102
	PREEMPTIBLE_HANDLER fp_disabled
103
 
104
/* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
105
.org trap_table + TT_FP_EXCEPTION_IEEE_754*ENTRY_SIZE
106
.global fb_exception_ieee_754_tl0
107
fp_exception_ieee_754_tl0:
108
	PREEMPTIBLE_HANDLER fp_exception_ieee_754
109
 
110
/* TT = 0x22, TL = 0, fb_exception_other handler */
111
.org trap_table + TT_FP_EXCEPTION_OTHER*ENTRY_SIZE
112
.global fb_exception_other_tl0
113
fp_exception_other_tl0:
114
	PREEMPTIBLE_HANDLER fp_exception_other
115
 
116
/* TT = 0x23, TL = 0, tag_overflow */
117
.org trap_table + TT_TAG_OVERFLOW*ENTRY_SIZE
118
.global tag_overflow_tl0
119
tag_overflow_tl0:
120
	PREEMPTIBLE_HANDLER tag_overflow
121
 
122
/* TT = 0x24, TL = 0, clean_window handler */
123
.org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
124
.global clean_window_tl0
125
clean_window_tl0:
126
	CLEAN_WINDOW_HANDLER
127
 
128
/* TT = 0x28, TL = 0, division_by_zero */
129
.org trap_table + TT_DIVISION_BY_ZERO*ENTRY_SIZE
130
.global division_by_zero_tl0
131
division_by_zero_tl0:
132
	PREEMPTIBLE_HANDLER division_by_zero
133
 
134
/* TT = 0x30, TL = 0, data_access_exception */
135
.org trap_table + TT_DATA_ACCESS_EXCEPTION*ENTRY_SIZE
136
.global data_access_exception_tl0
137
data_access_exception_tl0:
138
	/*wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
139
	PREEMPTIBLE_HANDLER data_access_exception*/
140
 
141
/* TT = 0x32, TL = 0, data_access_error */
142
.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
143
.global data_access_error_tl0
144
data_access_error_tl0:
145
	PREEMPTIBLE_HANDLER data_access_error
146
 
147
/* TT = 0x34, TL = 0, mem_address_not_aligned */
148
.org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
149
.global mem_address_not_aligned_tl0
150
mem_address_not_aligned_tl0:
151
	PREEMPTIBLE_HANDLER mem_address_not_aligned
152
 
153
/* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
154
.org trap_table + TT_LDDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
155
.global LDDF_mem_address_not_aligned_tl0
156
LDDF_mem_address_not_aligned_tl0:
157
	PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned
158
 
159
/* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
160
.org trap_table + TT_STDF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
161
.global STDF_mem_address_not_aligned_tl0
162
STDF_mem_address_not_aligned_tl0:
163
	PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned
164
 
165
/* TT = 0x37, TL = 0, privileged_action */
166
.org trap_table + TT_PRIVILEGED_ACTION*ENTRY_SIZE
167
.global privileged_action_tl0
168
privileged_action_tl0:
169
	PREEMPTIBLE_HANDLER privileged_action
170
 
171
/* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
172
.org trap_table + TT_LDQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
173
.global LDQF_mem_address_not_aligned_tl0
174
LDQF_mem_address_not_aligned_tl0:
175
	PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned
176
 
177
/* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
178
.org trap_table + TT_STQF_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
179
.global STQF_mem_address_not_aligned_tl0
180
STQF_mem_address_not_aligned_tl0:
181
	PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned
182
 
183
/* TT = 0x41, TL = 0, interrupt_level_1 handler */
184
.org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE
185
.global interrupt_level_1_handler_tl0
186
interrupt_level_1_handler_tl0:
187
	INTERRUPT_LEVEL_N_HANDLER 1
188
 
189
/* TT = 0x42, TL = 0, interrupt_level_2 handler */
190
.org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE
191
.global interrupt_level_2_handler_tl0
192
interrupt_level_2_handler_tl0:
193
	INTERRUPT_LEVEL_N_HANDLER 2
194
 
195
/* TT = 0x43, TL = 0, interrupt_level_3 handler */
196
.org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE
197
.global interrupt_level_3_handler_tl0
198
interrupt_level_3_handler_tl0:
199
	INTERRUPT_LEVEL_N_HANDLER 3
200
 
201
/* TT = 0x44, TL = 0, interrupt_level_4 handler */
202
.org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE
203
.global interrupt_level_4_handler_tl0
204
interrupt_level_4_handler_tl0:
205
	INTERRUPT_LEVEL_N_HANDLER 4
206
 
207
/* TT = 0x45, TL = 0, interrupt_level_5 handler */
208
.org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE
209
.global interrupt_level_5_handler_tl0
210
interrupt_level_5_handler_tl0:
211
	INTERRUPT_LEVEL_N_HANDLER 5
212
 
213
/* TT = 0x46, TL = 0, interrupt_level_6 handler */
214
.org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE
215
.global interrupt_level_6_handler_tl0
216
interrupt_level_6_handler_tl0:
217
	INTERRUPT_LEVEL_N_HANDLER 6
218
 
219
/* TT = 0x47, TL = 0, interrupt_level_7 handler */
220
.org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE
221
.global interrupt_level_7_handler_tl0
222
interrupt_level_7_handler_tl0:
223
	INTERRUPT_LEVEL_N_HANDLER 7
224
 
225
/* TT = 0x48, TL = 0, interrupt_level_8 handler */
226
.org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE
227
.global interrupt_level_8_handler_tl0
228
interrupt_level_8_handler_tl0:
229
	INTERRUPT_LEVEL_N_HANDLER 8
230
 
231
/* TT = 0x49, TL = 0, interrupt_level_9 handler */
232
.org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE
233
.global interrupt_level_9_handler_tl0
234
interrupt_level_9_handler_tl0:
235
	INTERRUPT_LEVEL_N_HANDLER 9
236
 
237
/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
238
.org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE
239
.global interrupt_level_10_handler_tl0
240
interrupt_level_10_handler_tl0:
241
	INTERRUPT_LEVEL_N_HANDLER 10
242
 
243
/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
244
.org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE
245
.global interrupt_level_11_handler_tl0
246
interrupt_level_11_handler_tl0:
247
	INTERRUPT_LEVEL_N_HANDLER 11
248
 
249
/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
250
.org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE
251
.global interrupt_level_12_handler_tl0
252
interrupt_level_12_handler_tl0:
253
	INTERRUPT_LEVEL_N_HANDLER 12
254
 
255
/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
256
.org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE
257
.global interrupt_level_13_handler_tl0
258
interrupt_level_13_handler_tl0:
259
	INTERRUPT_LEVEL_N_HANDLER 13
260
 
261
/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
262
.org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE
263
.global interrupt_level_14_handler_tl0
264
interrupt_level_14_handler_tl0:
265
	INTERRUPT_LEVEL_N_HANDLER 14
266
 
267
/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
268
.org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE
269
.global interrupt_level_15_handler_tl0
270
interrupt_level_15_handler_tl0:
271
	INTERRUPT_LEVEL_N_HANDLER 15
272
 
273
/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
274
.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
275
.global interrupt_vector_trap_handler_tl0
276
interrupt_vector_trap_handler_tl0:
277
	INTERRUPT_VECTOR_TRAP_HANDLER
278
 
279
/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
280
.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
281
.global fast_instruction_access_mmu_miss_handler_tl0
282
fast_instruction_access_mmu_miss_handler_tl0:
283
	/*FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER*/
284
 
285
/* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
286
.org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
287
.global fast_data_access_mmu_miss_handler_tl0
288
fast_data_access_mmu_miss_handler_tl0:
289
	FAST_DATA_ACCESS_MMU_MISS_HANDLER 0
290
 
291
/* TT = 0x6c, TL = 0, fast_data_access_protection */
292
.org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
293
.global fast_data_access_protection_handler_tl0
294
fast_data_access_protection_handler_tl0:
295
	/*FAST_DATA_ACCESS_PROTECTION_HANDLER 0*/
296
 
297
/* TT = 0x80, TL = 0, spill_0_normal handler */
298
.org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
299
.global spill_0_normal_tl0
300
spill_0_normal_tl0:
301
	SPILL_NORMAL_HANDLER_KERNEL
302
 
303
/* TT = 0x84, TL = 0, spill_1_normal handler */
304
.org trap_table + TT_SPILL_1_NORMAL*ENTRY_SIZE
305
.global spill_1_normal_tl0
306
spill_1_normal_tl0:
307
	SPILL_NORMAL_HANDLER_USERSPACE
308
 
309
/* TT = 0x88, TL = 0, spill_2_normal handler */
310
.org trap_table + TT_SPILL_2_NORMAL*ENTRY_SIZE
311
.global spill_2_normal_tl0
312
spill_2_normal_tl0:
313
	SPILL_TO_USPACE_WINDOW_BUFFER
314
 
315
/* TT = 0xa0, TL = 0, spill_0_other handler */
316
.org trap_table + TT_SPILL_0_OTHER*ENTRY_SIZE
317
.global spill_0_other_tl0
318
spill_0_other_tl0:
319
	SPILL_TO_USPACE_WINDOW_BUFFER
320
 
321
/* TT = 0xc0, TL = 0, fill_0_normal handler */
322
.org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE
323
.global fill_0_normal_tl0
324
fill_0_normal_tl0:
325
	FILL_NORMAL_HANDLER_KERNEL
326
 
327
/* TT = 0xc4, TL = 0, fill_1_normal handler */
328
.org trap_table + TT_FILL_1_NORMAL*ENTRY_SIZE
329
.global fill_1_normal_tl0
330
fill_1_normal_tl0:
331
	FILL_NORMAL_HANDLER_USERSPACE
332
 
333
/* TT = 0x100 - 0x17f, TL = 0, trap_instruction_0 - trap_instruction_7f */
334
.irp cur, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,\
335
    20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,\
336
    39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,\
337
    58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76,\
338
    77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,\
339
    96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\
340
    112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126,\
341
    127
342
.org trap_table + (TT_TRAP_INSTRUCTION_0+\cur)*ENTRY_SIZE
343
.global trap_instruction_\cur\()_tl0
344
trap_instruction_\cur\()_tl0:
345
	ba trap_instruction_handler
346
	mov \cur, %g2
347
.endr
348
 
349
/*
350
 * Handlers for TL>0.
351
 */
352
 
353
/* TT = 0x08, TL > 0, instruction_access_exception */
354
.org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
355
.global instruction_access_exception_tl1
356
instruction_access_exception_tl1:
357
	/*wrpr %g0, 1, %tl
358
	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
359
	PREEMPTIBLE_HANDLER instruction_access_exception*/
360
 
361
/* TT = 0x0a, TL > 0, instruction_access_error */
362
.org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE
363
.global instruction_access_error_tl1
364
instruction_access_error_tl1:
365
	wrpr %g0, 1, %tl
366
	PREEMPTIBLE_HANDLER instruction_access_error
367
 
368
/* TT = 0x10, TL > 0, illegal_instruction */
369
.org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
370
.global illegal_instruction_tl1
371
illegal_instruction_tl1:
372
	wrpr %g0, 1, %tl
373
	PREEMPTIBLE_HANDLER illegal_instruction
374
 
375
/* TT = 0x24, TL > 0, clean_window handler */
376
.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
377
.global clean_window_tl1
378
clean_window_tl1:
379
	CLEAN_WINDOW_HANDLER
380
 
381
/* TT = 0x28, TL > 0, division_by_zero */
382
.org trap_table + (TT_DIVISION_BY_ZERO+512)*ENTRY_SIZE
383
.global division_by_zero_tl1
384
division_by_zero_tl1:
385
	wrpr %g0, 1, %tl
386
	PREEMPTIBLE_HANDLER division_by_zero
387
 
388
/* TT = 0x30, TL > 0, data_access_exception */
389
.org trap_table + (TT_DATA_ACCESS_EXCEPTION+512)*ENTRY_SIZE
390
.global data_access_exception_tl1
391
data_access_exception_tl1:
392
	/*wrpr %g0, 1, %tl
393
	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
394
	PREEMPTIBLE_HANDLER data_access_exception*/
395
 
396
/* TT = 0x32, TL > 0, data_access_error */
397
.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
398
.global data_access_error_tl1
399
data_access_error_tl1:
400
	wrpr %g0, 1, %tl
401
	PREEMPTIBLE_HANDLER data_access_error
402
 
403
/* TT = 0x34, TL > 0, mem_address_not_aligned */
404
.org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE
405
.global mem_address_not_aligned_tl1
406
mem_address_not_aligned_tl1:
407
	wrpr %g0, 1, %tl
408
	PREEMPTIBLE_HANDLER mem_address_not_aligned
409
 
410
/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
411
.org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
412
.global fast_data_access_mmu_miss_handler_tl1
413
fast_data_access_mmu_miss_handler_tl1:
414
	FAST_DATA_ACCESS_MMU_MISS_HANDLER 1
415
 
416
/* TT = 0x6c, TL > 0, fast_data_access_protection */
417
.org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
418
.global fast_data_access_protection_handler_tl1
419
fast_data_access_protection_handler_tl1:
420
	/*FAST_DATA_ACCESS_PROTECTION_HANDLER 1*/
421
 
422
/* TT = 0x80, TL > 0, spill_0_normal handler */
423
.org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE
424
.global spill_0_normal_tl1
425
spill_0_normal_tl1:
426
	SPILL_NORMAL_HANDLER_KERNEL
427
 
428
/* TT = 0x88, TL > 0, spill_2_normal handler */
429
.org trap_table + (TT_SPILL_2_NORMAL+512)*ENTRY_SIZE
430
.global spill_2_normal_tl1
431
spill_2_normal_tl1:
432
	SPILL_TO_USPACE_WINDOW_BUFFER
433
 
434
/* TT = 0xa0, TL > 0, spill_0_other handler */
435
.org trap_table + (TT_SPILL_0_OTHER+512)*ENTRY_SIZE
436
.global spill_0_other_tl1
437
spill_0_other_tl1:
438
	SPILL_TO_USPACE_WINDOW_BUFFER
439
 
440
/* TT = 0xc0, TL > 0, fill_0_normal handler */
441
.org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE
442
.global fill_0_normal_tl1
443
fill_0_normal_tl1:
444
	FILL_NORMAL_HANDLER_KERNEL
445
 
446
.align TABLE_SIZE
447
 
448
 
449
#define NOT(x)	((x) == 0)
450
 
451
/* Preemptible trap handler for TL=1.
452
 *
453
 * This trap handler makes arrangements to make calling of scheduler() from
454
 * within a trap context possible. It is called from several other trap
455
 * handlers.
456
 *
457
 * This function can be entered either with interrupt globals or alternate
458
 * globals. Memory management trap handlers are obliged to switch to one of
459
 * those global sets prior to calling this function. Register window management
460
 * functions are not allowed to modify the alternate global registers.
461
 *
462
 * The kernel is designed to work on trap levels 0 - 4. For instance, the
463
 * following can happen:
464
 * TL0: kernel thread runs (CANSAVE=0, kernel stack not in DTLB)
465
 * TL1: preemptible trap handler started after a tick interrupt
466
 * TL2: preemptible trap handler did SAVE
467
 * TL3: spill handler touched the kernel stack  
468
 * TL4: hardware or software failure
469
 *
470
 * Input registers:
471
 *	%g1		Address of function to call if this is not a syscall.
472
 * 	%g2	 	First argument for the function.
473
 *	%g6		Pre-set as kernel stack base if trap from userspace.
474
 *	%g7		Pre-set as address of the userspace window buffer.
475
 */
476
.macro PREEMPTIBLE_HANDLER_TEMPLATE is_syscall
477
#if 0
478
	/*
479
	 * ASSERT(%tl == 1)
480
	 */
481
	rdpr %tl, %g3
482
	cmp %g3, 1
483
	be 1f
484
	nop
485
0:	ba 0b					! this is for debugging, if we ever get here
486
	nop					! it will be easy to find
487
 
488
1:
489
.if NOT(\is_syscall)
490
	rdpr %tstate, %g3
491
 
492
	/*
493
	 * One of the ways this handler can be invoked is after a nested MMU trap from
494
	 * either spill_1_normal or fill_1_normal traps. Both of these traps manipulate
495
	 * the CWP register. We deal with the situation by simulating the MMU trap
496
	 * on TL=1 and restart the respective SAVE or RESTORE instruction once the MMU
497
	 * trap is resolved. However, because we are in the wrong window from the
498
	 * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
499
	 */ 
500
	and %g3, TSTATE_CWP_MASK, %g4
501
	wrpr %g4, 0, %cwp			! resynchronize CWP
502
 
503
	andcc %g3, TSTATE_PRIV_BIT, %g0		! if this trap came from the privileged mode...
504
	bnz 0f					! ...skip setting of kernel stack and primary context
505
	nop
506
 
507
.endif
508
	/*
509
	 * Normal window spills will go to the userspace window buffer.
510
	 */
511
	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(2), %wstate
512
 
513
	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent unnecessary clean_window exceptions
514
 
515
	/*
516
	 * Switch to kernel stack. The old stack is
517
	 * automatically saved in the old window's %sp
518
	 * and the new window's %fp.
519
	 */
520
	save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
521
 
522
.if \is_syscall
523
	/*
524
	 * Copy arguments for the syscall to the new window.
525
	 */
526
	mov %i0, %o0
527
	mov %i1, %o1
528
	mov %i2, %o2
529
	mov %i3, %o3
530
	mov %i4, %o4
531
	mov %i5, %o5
532
.endif
533
 
534
	/*
535
	 * Mark the CANRESTORE windows as OTHER windows.
536
	 */
537
	rdpr %canrestore, %l0
538
	wrpr %l0, %otherwin
539
	wrpr %g0, %canrestore
540
 
541
	/*
542
	 * Switch to primary context 0.
543
	 */
544
	mov VA_PRIMARY_CONTEXT_REG, %l0
545
	stxa %g0, [%l0] ASI_DMMU
546
	rd %pc, %l0
547
	flush %l0
548
 
549
.if NOT(\is_syscall)
550
	ba 1f
551
	nop
552
0:
553
	save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
554
 
555
	/*
556
	 * At this moment, we are using the kernel stack 
557
	 * and have successfully allocated a register window.
558
	 */
559
1:
560
.endif
561
	/*
562
	 * Other window spills will go to the userspace window buffer
563
	 * and normal spills will go to the kernel stack.
564
	 */
565
	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
566
 
567
	/*
568
	 * Copy arguments.
569
	 */
570
	mov %g1, %l0
571
.if NOT(\is_syscall)
572
	mov %g2, %o0
573
.else
574
	! store the syscall number on the stack as 7th argument
575
	stx %g2, [%sp + STACK_WINDOW_SAVE_AREA_SIZE + STACK_BIAS + STACK_ARG6] 
576
.endif
577
 
578
	/*
579
	 * Save TSTATE, TPC and TNPC aside.
580
	 */
581
	rdpr %tstate, %g1
582
	rdpr %tpc, %g2
583
	rdpr %tnpc, %g3
584
	rd %y, %g4
585
 
586
	stx %g1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE]
587
	stx %g2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC]
588
	stx %g3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC]
589
 
590
	/*
591
	 * Save the Y register.
592
	 * This register is deprecated according to SPARC V9 specification
593
	 * and is only present for backward compatibility with previous
594
	 * versions of the SPARC architecture.
595
	 * Surprisingly, gcc makes use of this register without a notice.
596
	 */
597
	stx %g4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y]
598
 
599
	wrpr %g0, 0, %tl
600
	wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate
601
	SAVE_GLOBALS
602
 
603
.if NOT(\is_syscall)
604
	/*
605
	 * Call the higher-level handler and pass istate as second parameter.
606
	 */
607
	call %l0
608
	add %sp, PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC, %o1
609
.else
610
	/*
611
	 * Call the higher-level syscall handler.
612
	 */
613
	call syscall_handler
614
	nop
615
	mov %o0, %i0				! copy the value returned by the syscall
616
.endif
617
 
618
	RESTORE_GLOBALS
619
	rdpr %pstate, %l1			! we must preserve the PEF bit
620
	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
621
	wrpr %g0, 1, %tl
622
 
623
	/*
624
	 * Read TSTATE, TPC and TNPC from saved copy.
625
	 */
626
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TSTATE], %g1
627
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TPC], %g2
628
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_TNPC], %g3
629
 
630
	/*
631
	 * Copy PSTATE.PEF to the in-register copy of TSTATE.
632
	 */
633
	and %l1, PSTATE_PEF_BIT, %l1
634
	sllx %l1, TSTATE_PSTATE_SHIFT, %l1
635
	sethi %hi(TSTATE_PEF_BIT), %g4
636
	andn %g1, %g4, %g1
637
	or %g1, %l1, %g1
638
 
639
	/*
640
	 * Restore TSTATE, TPC and TNPC from saved copies.
641
	 */
642
	wrpr %g1, 0, %tstate
643
	wrpr %g2, 0, %tpc
644
	wrpr %g3, 0, %tnpc
645
 
646
	/*
647
	 * Restore Y.
648
	 */
649
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_Y], %g4
650
	wr %g4, %y
651
 
652
	/*
653
	 * If OTHERWIN is zero, then all the userspace windows have been
654
	 * spilled to kernel memory (i.e. register window buffer). Moreover,
655
	 * if the scheduler was called in the meantime, all valid windows
656
	 * belonging to other threads were spilled by context_restore().
657
	 * If OTHERWIN is non-zero, then some userspace windows are still
658
	 * valid. Others might have been spilled. However, the CWP pointer
659
	 * needs no fixing because the scheduler had not been called.
660
	 */
661
	rdpr %otherwin, %l0
662
	brnz %l0, 0f
663
	nop
664
 
665
	/*
666
	 * OTHERWIN == 0
667
	 */
668
 
669
	/*
670
	 * If TSTATE.CWP + 1 == CWP, then we still do not have to fix CWP.
671
	 */
672
	and %g1, TSTATE_CWP_MASK, %l0
673
	inc %l0
674
	and %l0, NWINDOWS - 1, %l0	! %l0 mod NWINDOWS
675
	rdpr %cwp, %l1
676
	cmp %l0, %l1
677
	bz 0f				! CWP is ok
678
	nop
679
 
680
	/*
681
	 * Fix CWP.
682
	 * In order to recapitulate, the input registers in the current
683
	 * window are the output registers of the window to which we want
684
	 * to restore. Because the fill trap fills only input and local
685
	 * registers of a window, we need to preserve those output
686
	 * registers manually.
687
	 */
688
	mov %sp, %g2
689
	stx %i0, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0]
690
	stx %i1, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1]
691
	stx %i2, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2]
692
	stx %i3, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3]
693
	stx %i4, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4]
694
	stx %i5, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5]
695
	stx %i6, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6]
696
	stx %i7, [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7]
697
	wrpr %l0, 0, %cwp
698
	mov %g2, %sp
699
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I0], %i0
700
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I1], %i1
701
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I2], %i2
702
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I3], %i3
703
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I4], %i4
704
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I5], %i5
705
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I6], %i6
706
	ldx [%sp + PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE + STACK_BIAS + SAVED_I7], %i7
707
 
708
	/*
709
	 * OTHERWIN != 0 or fall-through from the OTHERWIN == 0 case.
710
	 * The CWP has already been restored to the value it had after the SAVE
711
	 * at the beginning of this function.
712
	 */
713
0:
714
.if NOT(\is_syscall)
715
	rdpr %tstate, %g1
716
	andcc %g1, TSTATE_PRIV_BIT, %g0		! if we are not returning to userspace...,
717
	bnz 1f					! ...skip restoring userspace windows
718
	nop
719
.endif
720
 
721
	/*
722
	 * Spills and fills will be processed by the {spill,fill}_1_normal
723
	 * handlers.
724
	 */
725
	wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate
726
 
727
	/*
728
	 * Set primary context according to secondary context.
729
	 */
730
	wr %g0, ASI_DMMU, %asi
731
	ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1
732
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi
733
	rd %pc, %g1
734
	flush %g1
735
 
736
	rdpr %cwp, %g1
737
	rdpr %otherwin, %g2
738
 
739
	/*
740
	 * Skip all OTHERWIN windows and descend to the first window
741
	 * in the userspace window buffer.
742
	 */
743
	sub %g1, %g2, %g3
744
	dec %g3
745
	and %g3, NWINDOWS - 1, %g3
746
	wrpr %g3, 0, %cwp
747
 
748
	/*
749
	 * CWP is now in the window last saved in the userspace window buffer.
750
	 * Fill all windows stored in the buffer.
751
	 */
752
	clr %g4
753
0:	andcc %g7, UWB_ALIGNMENT - 1, %g0	! alignment check
754
	bz 0f					! %g7 is UWB_ALIGNMENT-aligned, no more windows to refill
755
	nop
756
 
757
	add %g7, -STACK_WINDOW_SAVE_AREA_SIZE, %g7
758
	ldx [%g7 + L0_OFFSET], %l0
759
	ldx [%g7 + L1_OFFSET], %l1
760
	ldx [%g7 + L2_OFFSET], %l2
761
	ldx [%g7 + L3_OFFSET], %l3
762
	ldx [%g7 + L4_OFFSET], %l4
763
	ldx [%g7 + L5_OFFSET], %l5
764
	ldx [%g7 + L6_OFFSET], %l6
765
	ldx [%g7 + L7_OFFSET], %l7
766
	ldx [%g7 + I0_OFFSET], %i0
767
	ldx [%g7 + I1_OFFSET], %i1
768
	ldx [%g7 + I2_OFFSET], %i2
769
	ldx [%g7 + I3_OFFSET], %i3
770
	ldx [%g7 + I4_OFFSET], %i4
771
	ldx [%g7 + I5_OFFSET], %i5
772
	ldx [%g7 + I6_OFFSET], %i6
773
	ldx [%g7 + I7_OFFSET], %i7
774
 
775
	dec %g3
776
	and %g3, NWINDOWS - 1, %g3
777
	wrpr %g3, 0, %cwp			! switch to the preceeding window
778
 
779
	ba 0b
780
	inc %g4
781
 
782
0:
783
	/*
784
	 * Switch back to the proper current window and adjust
785
	 * OTHERWIN, CANRESTORE, CANSAVE and CLEANWIN.
786
	 */
787
	wrpr %g1, 0, %cwp
788
	add %g4, %g2, %g2
789
	cmp %g2, NWINDOWS - 2
790
	bg 2f					! fix the CANRESTORE=NWINDOWS-1 anomaly
791
	mov NWINDOWS - 2, %g1			! use dealy slot for both cases
792
	sub %g1, %g2, %g1
793
 
794
	wrpr %g0, 0, %otherwin
795
	wrpr %g1, 0, %cansave			! NWINDOWS - 2 - CANRESTORE
796
	wrpr %g2, 0, %canrestore		! OTHERWIN + windows in the buffer
797
	wrpr %g2, 0, %cleanwin			! avoid information leak
798
 
799
1:
800
	restore
801
 
802
.if \is_syscall
803
	done
804
.else
805
	retry
806
.endif
807
 
808
	/*
809
	 * We got here in order to avoid inconsistency of the window state registers.
810
	 * If the:
811
	 *
812
	 * 	save %g6, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
813
	 *
814
	 * instruction trapped and spilled a register window into the userspace
815
	 * window buffer, we have just restored NWINDOWS - 1 register windows.
816
	 * However, CANRESTORE can be only NWINDOW - 2 at most.
817
	 *
818
	 * The solution is to manually switch to (CWP - 1) mod NWINDOWS
819
	 * and set the window state registers so that:
820
	 *
821
	 * 	CANRESTORE 	= NWINDOWS - 2
822
	 *	CLEANWIN	= NWINDOWS - 2
823
	 *	CANSAVE 	= 0
824
	 *	OTHERWIN	= 0
825
	 *
826
	 * The RESTORE instruction is therfore to be skipped.
827
	 */
828
2:
829
	wrpr %g0, 0, %otherwin
830
	wrpr %g0, 0, %cansave
831
	wrpr %g1, 0, %canrestore
832
	wrpr %g1, 0, %cleanwin
833
 
834
	rdpr %cwp, %g1
835
	dec %g1
836
	and %g1, NWINDOWS - 1, %g1
837
	wrpr %g1, 0, %cwp			! CWP--
838
 
839
.if \is_syscall
840
	done
841
.else
842
	retry
843
.endif
844
 
845
#endif
846
.endm
847
 
848
.global preemptible_handler
849
preemptible_handler:
850
	PREEMPTIBLE_HANDLER_TEMPLATE 0
851
 
852
.global trap_instruction_handler
853
trap_instruction_handler:
854
	PREEMPTIBLE_HANDLER_TEMPLATE 1