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3743 rimsky 1
#
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# Copyright (c) 2005 Jakub Jermar
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#include <arch/arch.h>
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#include <arch/sun4u/arch.h>
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#include <arch/cpu.h>
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#include <arch/sun4u/regdef.h>
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#include <arch/boot/boot.h>
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#include <arch/stack.h>
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#include <arch/mm/sun4u/mmu.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/sun4u/tlb.h>
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#include <arch/mm/sun4u/tte.h>
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#ifdef CONFIG_SMP
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#include <arch/context_offset.h>
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#endif
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.register %g2, #scratch
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.register %g3, #scratch
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48
.section K_TEXT_START, "ax"
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50
#define BSP_FLAG	1
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52
/*
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 * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on
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 * a given processor.
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 */
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#if defined (US)
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    #define PHYSMEM_ADDR_SIZE	41
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#elif defined (US3)
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    #define PHYSMEM_ADDR_SIZE	43
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#endif
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/*
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 * Here is where the kernel is passed control from the boot loader.
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 * 
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 * The registers are expected to be in this state:
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 * - %o0 starting address of physical memory + bootstrap processor flag
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 * 	bits 63...1:	physical memory starting address / 2
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 *	bit 0:		non-zero on BSP processor, zero on AP processors
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 * - %o1 bootinfo structure address (BSP only)
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 * - %o2 bootinfo structure size (BSP only)
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 *
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 * Moreover, we depend on boot having established the following environment:
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 * - TLBs are on
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 * - identity mapping for the kernel image
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 */
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77
.global kernel_image_start
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kernel_image_start:
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	mov BSP_FLAG, %l0
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	and %o0, %l0, %l7			! l7 <= bootstrap processor?
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	andn %o0, %l0, %l6			! l6 <= start of physical memory
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83
	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
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	srlx %l6, 13, %l5
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86
	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
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	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
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	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5	
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90
	/*
91
	 * Setup basic runtime environment.
92
	 */
93
 
94
	wrpr %g0, NWINDOWS - 2, %cansave	! set maximum saveable windows
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	wrpr %g0, 0, %canrestore		! get rid of windows we will
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						! never need again
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	wrpr %g0, 0, %otherwin			! make sure the window state is
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						! consistent
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	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window
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						! traps for kernel
101
 
102
	wrpr %g0, 0, %wstate			! use default spill/fill trap
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104
	wrpr %g0, 0, %tl			! TL = 0, primary context
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						! register is used
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107
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! disable interrupts and disable
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						! 32-bit address masking
109
 
110
	wrpr %g0, 0, %pil			! intialize %pil
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112
	/*
113
	 * Switch to kernel trap table.
114
	 */
115
	sethi %hi(trap_table), %g1
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	wrpr %g1, %lo(trap_table), %tba
117
 
118
	/* 
119
	 * Take over the DMMU by installing locked TTE entry identically
120
	 * mapping the first 4M of memory.
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	 *
122
	 * In case of DMMU, no FLUSH instructions need to be issued. Because of
123
	 * that, the old DTLB contents can be demapped pretty straightforwardly
124
	 * and without causing any traps.
125
	 */
126
 
127
	wr %g0, ASI_DMMU, %asi
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129
#define SET_TLB_DEMAP_CMD(r1, context_id) \
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	set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \
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		TLB_DEMAP_CONTEXT_SHIFT), %r1
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133
	! demap context 0
134
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
135
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
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	membar #Sync
137
 
138
#define SET_TLB_TAG(r1, context) \
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	set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
140
 
141
	! write DTLB tag
142
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
143
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
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	membar #Sync
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146
#ifdef CONFIG_VIRT_IDX_DCACHE
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#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_CV | TTE_P | LMA | (imm))
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#else /* CONFIG_VIRT_IDX_DCACHE */
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#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_P | LMA | (imm))
150
#endif /* CONFIG_VIRT_IDX_DCACHE */
151
 
152
#define SET_TLB_DATA(r1, r2, imm) \
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	set TTE_LOW_DATA(imm), %r1; \
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	or %r1, %l5, %r1; \
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	mov PAGESIZE_4M, %r2; \
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	sllx %r2, TTE_SIZE_SHIFT, %r2; \
157
	or %r1, %r2, %r1; \
158
	mov 1, %r2; \
159
	sllx %r2, TTE_V_SHIFT, %r2; \
160
	or %r1, %r2, %r1;
161
 
162
	! write DTLB data and install the kernel mapping
163
	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
164
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
165
	membar #Sync
166
 
167
	/*
168
	 * Because we cannot use global mappings (because we want to have
169
	 * separate 64-bit address spaces for both the kernel and the
170
	 * userspace), we prepare the identity mapping also in context 1. This
171
	 * step is required by the code installing the ITLB mapping.
172
	 */
173
	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
174
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
175
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
176
	membar #Sync
177
 
178
	! write DTLB data and install the kernel mapping in context 1
179
	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
180
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
181
	membar #Sync
182
 
183
	/*
184
	 * Now is time to take over the IMMU. Unfortunatelly, it cannot be done
185
	 * as easily as the DMMU, because the IMMU is mapping the code it
186
	 * executes.
187
	 *
188
	 * [ Note that brave experiments with disabling the IMMU and using the
189
	 * DMMU approach failed after a dozen of desparate days with only little
190
	 * success. ]
191
	 *
192
	 * The approach used here is inspired from OpenBSD. First, the kernel
193
	 * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and
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	 * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
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	 * afterwards and replaced with the kernel permanent mapping. Finally,
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	 * the kernel switches back to context 0 and demaps context 1.
197
	 *
198
	 * Moreover, the IMMU requires use of the FLUSH instructions. But that
199
	 * is OK because we always use operands with addresses already mapped by
200
	 * the taken over DTLB.
201
	 */
202
 
203
	set kernel_image_start, %g5
204
 
205
	! write ITLB tag of context 1
206
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
207
	mov VA_DMMU_TAG_ACCESS, %g2
208
	stxa %g1, [%g2] ASI_IMMU
209
	flush %g5
210
 
211
	! write ITLB data and install the temporary mapping in context 1
212
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
213
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
214
	flush %g5
215
 
216
	! switch to context 1
217
	mov MEM_CONTEXT_TEMP, %g1
218
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
219
	flush %g5
220
 
221
	! demap context 0
222
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
223
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
224
	flush %g5
225
 
226
	! write ITLB tag of context 0
227
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
228
	mov VA_DMMU_TAG_ACCESS, %g2
229
	stxa %g1, [%g2] ASI_IMMU
230
	flush %g5
231
 
232
	! write ITLB data and install the permanent kernel mapping in context 0
233
	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
234
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
235
	flush %g5
236
 
237
	! enter nucleus - using context 0
238
	wrpr %g0, 1, %tl
239
 
240
	! demap context 1
241
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
242
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
243
	flush %g5
244
 
245
	! set context 0 in the primary context register
246
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
247
	flush %g5
248
 
249
	! leave nucleus - using primary context, i.e. context 0
250
	wrpr %g0, 0, %tl
251
 
252
	brz %l7, 1f				! skip if you are not the bootstrap CPU
253
	nop
254
 
255
	/*
256
	 * Save physmem_base for use by the mm subsystem.
257
	 * %l6 contains starting physical address
258
	 */
259
	sethi %hi(physmem_base), %l4
260
	stx %l6, [%l4 + %lo(physmem_base)]
261
 
262
	/*
263
	 * Precompute kernel 8K TLB data template.
264
	 * %l5 contains starting physical address
265
	 * bits [(PHYSMEM_ADDR_SIZE - 1):13]
266
	 */
267
	sethi %hi(kernel_8k_tlb_data_template), %l4
268
	ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
269
	or %l3, %l5, %l3
270
	stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
271
 
272
	/*
273
	 * Flush D-Cache.
274
	 */
275
	call dcache_flush
276
	nop
277
 
278
	/*
279
	 * So far, we have not touched the stack.
280
	 * It is a good idea to set the kernel stack to a known state now.
281
	 */
282
	sethi %hi(temporary_boot_stack), %sp
283
	or %sp, %lo(temporary_boot_stack), %sp
284
	sub %sp, STACK_BIAS, %sp
285
 
286
	sethi 0x42142, %g0
287
	sethi %hi(bootinfo), %o0
288
	call memcpy				! copy bootinfo
289
	or %o0, %lo(bootinfo), %o0
290
 
291
	call arch_pre_main
292
	nop
293
 
294
	call main_bsp
295
	nop
296
 
297
	/* Not reached. */
298
 
299
0:
300
	ba 0b
301
	nop
302
 
303
 
304
1:
305
#ifdef CONFIG_SMP
306
	/*
307
	 * Determine the width of the MID and save its mask to %g3. The width
308
	 * is
309
	 * 	* 5 for US and US-IIIi,
310
	 * 	* 10 for US3 except US-IIIi.
311
	 */
312
#if defined(US)
313
	mov 0x1f, %g3
314
#elif defined(US3)
315
	mov 0x3ff, %g3
316
	rdpr %ver, %g2
317
	sllx %g2, 16, %g2
318
	srlx %g2, 48, %g2
319
	cmp %g2, IMPL_ULTRASPARCIII_I
320
	move %xcc, 0x1f, %g3
321
#endif
322
 
323
	/*
324
	 * Read MID from the processor.
325
	 */
326
	ldxa [%g0] ASI_ICBUS_CONFIG, %g1
327
	srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
328
	and %g1, %g3, %g1
329
 
330
	/*
331
	 * Active loop for APs until the BSP picks them up. A processor cannot
332
	 * leave the loop until the global variable 'waking_up_mid' equals its
333
	 * MID.
334
	 */
335
	set waking_up_mid, %g2
336
2:
337
	ldx [%g2], %g3
338
	cmp %g3, %g1
339
	bne 2b
340
	nop
341
 
342
	/*
343
	 * Configure stack for the AP.
344
	 * The AP is expected to use the stack saved
345
	 * in the ctx global variable.
346
	 */
347
	set ctx, %g1
348
	add %g1, OFFSET_SP, %g1
349
	ldx [%g1], %o6
350
 
351
	call main_ap
352
	nop
353
 
354
	/* Not reached. */
355
#endif
356
 
357
0:
358
	ba 0b
359
	nop
360
 
361
 
362
.section K_DATA_START, "aw", @progbits
363
 
364
/*
365
 * Create small stack to be used by the bootstrap processor. It is going to be
366
 * used only for a very limited period of time, but we switch to it anyway,
367
 * just to be sure we are properly initialized.
368
 */
369
 
370
#define INITIAL_STACK_SIZE	1024
371
 
372
.align STACK_ALIGNMENT
373
	.space INITIAL_STACK_SIZE
374
.align STACK_ALIGNMENT
375
temporary_boot_stack:
376
	.space STACK_WINDOW_SAVE_AREA_SIZE
377
 
378
 
379
.data
380
 
381
.align 8
382
.global physmem_base		! copy of the physical memory base address
383
physmem_base:
384
	.quad 0
385
 
386
/*
387
 * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it
388
 * is further modified to reflect the starting address of physical memory.
389
 */
390
.global kernel_8k_tlb_data_template
391
kernel_8k_tlb_data_template:
392
#ifdef CONFIG_VIRT_IDX_DCACHE
393
	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
394
		 TTE_CV | TTE_P | TTE_W)
395
#else /* CONFIG_VIRT_IDX_DCACHE */
396
	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
397
		TTE_P | TTE_W)
398
#endif /* CONFIG_VIRT_IDX_DCACHE */
399