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418 | jermar | 1 | # |
2071 | jermar | 2 | # Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | # All rights reserved. |
4 | # |
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5 | # Redistribution and use in source and binary forms, with or without |
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6 | # modification, are permitted provided that the following conditions |
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7 | # are met: |
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8 | # |
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9 | # - Redistributions of source code must retain the above copyright |
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10 | # notice, this list of conditions and the following disclaimer. |
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11 | # - Redistributions in binary form must reproduce the above copyright |
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12 | # notice, this list of conditions and the following disclaimer in the |
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13 | # documentation and/or other materials provided with the distribution. |
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14 | # - The name of the author may not be used to endorse or promote products |
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15 | # derived from this software without specific prior written permission. |
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16 | # |
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17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | # |
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28 | |||
1903 | jermar | 29 | #include <arch/arch.h> |
1789 | jermar | 30 | #include <arch/regdef.h> |
1823 | jermar | 31 | #include <arch/boot/boot.h> |
1917 | jermar | 32 | #include <arch/stack.h> |
846 | jermar | 33 | |
1823 | jermar | 34 | #include <arch/mm/mmu.h> |
35 | #include <arch/mm/tlb.h> |
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36 | #include <arch/mm/tte.h> |
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37 | |||
1903 | jermar | 38 | #ifdef CONFIG_SMP |
39 | #include <arch/context_offset.h> |
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40 | #endif |
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41 | |||
426 | jermar | 42 | .register %g2, #scratch |
43 | .register %g3, #scratch |
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44 | |||
418 | jermar | 45 | .section K_TEXT_START, "ax" |
46 | |||
1978 | jermar | 47 | #define BSP_FLAG 1 |
48 | |||
847 | jermar | 49 | /* |
3365 | rimsky | 50 | * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on |
51 | * a given processor. |
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52 | */ |
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3398 | rimsky | 53 | #if defined (US) |
3365 | rimsky | 54 | #define PHYSMEM_ADDR_SIZE 41 |
55 | #elif defined (US3) |
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56 | #define PHYSMEM_ADDR_SIZE 43 |
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57 | #endif |
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58 | |||
59 | /* |
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1978 | jermar | 60 | * Here is where the kernel is passed control from the boot loader. |
1790 | jermar | 61 | * |
62 | * The registers are expected to be in this state: |
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1978 | jermar | 63 | * - %o0 starting address of physical memory + bootstrap processor flag |
64 | * bits 63...1: physical memory starting address / 2 |
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65 | * bit 0: non-zero on BSP processor, zero on AP processors |
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66 | * - %o1 bootinfo structure address (BSP only) |
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67 | * - %o2 bootinfo structure size (BSP only) |
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1792 | jermar | 68 | * |
1978 | jermar | 69 | * Moreover, we depend on boot having established the following environment: |
1792 | jermar | 70 | * - TLBs are on |
71 | * - identity mapping for the kernel image |
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847 | jermar | 72 | */ |
73 | |||
418 | jermar | 74 | .global kernel_image_start |
75 | kernel_image_start: |
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1978 | jermar | 76 | mov BSP_FLAG, %l0 |
2001 | jermar | 77 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
78 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
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846 | jermar | 79 | |
3365 | rimsky | 80 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. |
1982 | jermar | 81 | srlx %l6, 13, %l5 |
1978 | jermar | 82 | |
3365 | rimsky | 83 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
84 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
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85 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
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86 | |||
1978 | jermar | 87 | /* |
1823 | jermar | 88 | * Setup basic runtime environment. |
1790 | jermar | 89 | */ |
424 | jermar | 90 | |
1954 | jermar | 91 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
2049 | jermar | 92 | wrpr %g0, 0, %canrestore ! get rid of windows we will |
93 | ! never need again |
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94 | wrpr %g0, 0, %otherwin ! make sure the window state is |
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95 | ! consistent |
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96 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
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97 | ! traps for kernel |
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3365 | rimsky | 98 | |
99 | wrpr %g0, 0, %wstate ! use the default spill/fill trap |
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1823 | jermar | 100 | |
2049 | jermar | 101 | wrpr %g0, 0, %tl ! TL = 0, primary context |
102 | ! register is used |
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1823 | jermar | 103 | |
2049 | jermar | 104 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable |
105 | ! 32-bit address masking |
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1823 | jermar | 106 | |
1881 | jermar | 107 | wrpr %g0, 0, %pil ! intialize %pil |
108 | |||
1790 | jermar | 109 | /* |
1823 | jermar | 110 | * Switch to kernel trap table. |
111 | */ |
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1880 | jermar | 112 | sethi %hi(trap_table), %g1 |
113 | wrpr %g1, %lo(trap_table), %tba |
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1823 | jermar | 114 | |
115 | /* |
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2078 | jermar | 116 | * Take over the DMMU by installing locked TTE entry identically |
2049 | jermar | 117 | * mapping the first 4M of memory. |
1792 | jermar | 118 | * |
2049 | jermar | 119 | * In case of DMMU, no FLUSH instructions need to be issued. Because of |
120 | * that, the old DTLB contents can be demapped pretty straightforwardly |
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121 | * and without causing any traps. |
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1792 | jermar | 122 | */ |
123 | |||
1823 | jermar | 124 | wr %g0, ASI_DMMU, %asi |
895 | jermar | 125 | |
1823 | jermar | 126 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
2049 | jermar | 127 | set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ |
128 | TLB_DEMAP_CONTEXT_SHIFT), %r1 |
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1823 | jermar | 129 | |
130 | ! demap context 0 |
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131 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
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132 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
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133 | membar #Sync |
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134 | |||
135 | #define SET_TLB_TAG(r1, context) \ |
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2049 | jermar | 136 | set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
1823 | jermar | 137 | |
138 | ! write DTLB tag |
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139 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
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140 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
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141 | membar #Sync |
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142 | |||
2009 | jermar | 143 | #ifdef CONFIG_VIRT_IDX_DCACHE |
1996 | jermar | 144 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) |
2009 | jermar | 145 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
1996 | jermar | 146 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) |
2009 | jermar | 147 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
1996 | jermar | 148 | |
1823 | jermar | 149 | #define SET_TLB_DATA(r1, r2, imm) \ |
1996 | jermar | 150 | set TTE_LOW_DATA(imm), %r1; \ |
1978 | jermar | 151 | or %r1, %l5, %r1; \ |
152 | mov PAGESIZE_4M, %r2; \ |
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1823 | jermar | 153 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
154 | or %r1, %r2, %r1; \ |
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1880 | jermar | 155 | mov 1, %r2; \ |
1823 | jermar | 156 | sllx %r2, TTE_V_SHIFT, %r2; \ |
157 | or %r1, %r2, %r1; |
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158 | |||
159 | ! write DTLB data and install the kernel mapping |
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1887 | jermar | 160 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
1823 | jermar | 161 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
162 | membar #Sync |
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1868 | jermar | 163 | |
164 | /* |
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2049 | jermar | 165 | * Because we cannot use global mappings (because we want to have |
166 | * separate 64-bit address spaces for both the kernel and the |
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167 | * userspace), we prepare the identity mapping also in context 1. This |
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168 | * step is required by the code installing the ITLB mapping. |
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1868 | jermar | 169 | */ |
170 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
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171 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
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172 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
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173 | membar #Sync |
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174 | |||
175 | ! write DTLB data and install the kernel mapping in context 1 |
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1887 | jermar | 176 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
1868 | jermar | 177 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
178 | membar #Sync |
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1823 | jermar | 179 | |
180 | /* |
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2049 | jermar | 181 | * Now is time to take over the IMMU. Unfortunatelly, it cannot be done |
182 | * as easily as the DMMU, because the IMMU is mapping the code it |
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183 | * executes. |
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1823 | jermar | 184 | * |
2049 | jermar | 185 | * [ Note that brave experiments with disabling the IMMU and using the |
186 | * DMMU approach failed after a dozen of desparate days with only little |
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187 | * success. ] |
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1823 | jermar | 188 | * |
2049 | jermar | 189 | * The approach used here is inspired from OpenBSD. First, the kernel |
190 | * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and |
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191 | * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
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192 | * afterwards and replaced with the kernel permanent mapping. Finally, |
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193 | * the kernel switches back to context 0 and demaps context 1. |
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1823 | jermar | 194 | * |
2049 | jermar | 195 | * Moreover, the IMMU requires use of the FLUSH instructions. But that |
196 | * is OK because we always use operands with addresses already mapped by |
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197 | * the taken over DTLB. |
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1823 | jermar | 198 | */ |
199 | |||
1852 | jermar | 200 | set kernel_image_start, %g5 |
1823 | jermar | 201 | |
202 | ! write ITLB tag of context 1 |
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203 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
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1880 | jermar | 204 | mov VA_DMMU_TAG_ACCESS, %g2 |
1823 | jermar | 205 | stxa %g1, [%g2] ASI_IMMU |
1852 | jermar | 206 | flush %g5 |
1823 | jermar | 207 | |
208 | ! write ITLB data and install the temporary mapping in context 1 |
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209 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
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210 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
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1852 | jermar | 211 | flush %g5 |
1823 | jermar | 212 | |
213 | ! switch to context 1 |
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1880 | jermar | 214 | mov MEM_CONTEXT_TEMP, %g1 |
1823 | jermar | 215 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
1852 | jermar | 216 | flush %g5 |
1823 | jermar | 217 | |
218 | ! demap context 0 |
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219 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
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220 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
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1852 | jermar | 221 | flush %g5 |
1823 | jermar | 222 | |
223 | ! write ITLB tag of context 0 |
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224 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
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1880 | jermar | 225 | mov VA_DMMU_TAG_ACCESS, %g2 |
1823 | jermar | 226 | stxa %g1, [%g2] ASI_IMMU |
1852 | jermar | 227 | flush %g5 |
1823 | jermar | 228 | |
229 | ! write ITLB data and install the permanent kernel mapping in context 0 |
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1887 | jermar | 230 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
1823 | jermar | 231 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
1852 | jermar | 232 | flush %g5 |
1823 | jermar | 233 | |
1906 | jermar | 234 | ! enter nucleus - using context 0 |
1823 | jermar | 235 | wrpr %g0, 1, %tl |
236 | |||
237 | ! demap context 1 |
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238 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
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239 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
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1852 | jermar | 240 | flush %g5 |
1823 | jermar | 241 | |
242 | ! set context 0 in the primary context register |
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243 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
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1852 | jermar | 244 | flush %g5 |
1823 | jermar | 245 | |
1906 | jermar | 246 | ! leave nucleus - using primary context, i.e. context 0 |
1823 | jermar | 247 | wrpr %g0, 0, %tl |
1864 | jermar | 248 | |
1903 | jermar | 249 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
250 | nop |
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1900 | jermar | 251 | |
1917 | jermar | 252 | /* |
1982 | jermar | 253 | * Save physmem_base for use by the mm subsystem. |
254 | * %l6 contains starting physical address |
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255 | */ |
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256 | sethi %hi(physmem_base), %l4 |
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257 | stx %l6, [%l4 + %lo(physmem_base)] |
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258 | |||
259 | /* |
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260 | * Precompute kernel 8K TLB data template. |
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3365 | rimsky | 261 | * %l5 contains starting physical address |
262 | * bits [(PHYSMEM_ADDR_SIZE - 1):13] |
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1982 | jermar | 263 | */ |
264 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
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265 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
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266 | or %l3, %l5, %l3 |
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267 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
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268 | |||
269 | /* |
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2008 | jermar | 270 | * Flush D-Cache. |
271 | */ |
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272 | call dcache_flush |
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273 | nop |
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274 | |||
275 | /* |
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1917 | jermar | 276 | * So far, we have not touched the stack. |
1975 | jermar | 277 | * It is a good idea to set the kernel stack to a known state now. |
1917 | jermar | 278 | */ |
279 | sethi %hi(temporary_boot_stack), %sp |
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280 | or %sp, %lo(temporary_boot_stack), %sp |
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281 | sub %sp, STACK_BIAS, %sp |
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282 | |||
1906 | jermar | 283 | sethi %hi(bootinfo), %o0 |
284 | call memcpy ! copy bootinfo |
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285 | or %o0, %lo(bootinfo), %o0 |
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286 | |||
1864 | jermar | 287 | call arch_pre_main |
288 | nop |
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1823 | jermar | 289 | |
426 | jermar | 290 | call main_bsp |
291 | nop |
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292 | |||
293 | /* Not reached. */ |
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294 | |||
1903 | jermar | 295 | 0: |
296 | ba 0b |
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297 | nop |
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298 | |||
299 | |||
300 | /* |
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301 | * Read MID from the processor. |
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302 | */ |
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303 | 1: |
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3479 | rimsky | 304 | ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
305 | srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
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306 | and %g1, ICBUS_CONFIG_MID_MASK, %g1 |
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1903 | jermar | 307 | |
1905 | jermar | 308 | #ifdef CONFIG_SMP |
1903 | jermar | 309 | /* |
2049 | jermar | 310 | * Active loop for APs until the BSP picks them up. A processor cannot |
311 | * leave the loop until the global variable 'waking_up_mid' equals its |
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1903 | jermar | 312 | * MID. |
313 | */ |
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314 | set waking_up_mid, %g2 |
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424 | jermar | 315 | 2: |
1903 | jermar | 316 | ldx [%g2], %g3 |
317 | cmp %g3, %g1 |
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318 | bne 2b |
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424 | jermar | 319 | nop |
1903 | jermar | 320 | |
321 | /* |
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322 | * Configure stack for the AP. |
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323 | * The AP is expected to use the stack saved |
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324 | * in the ctx global variable. |
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325 | */ |
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326 | set ctx, %g1 |
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327 | add %g1, OFFSET_SP, %g1 |
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328 | ldx [%g1], %o6 |
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329 | |||
330 | call main_ap |
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331 | nop |
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332 | |||
333 | /* Not reached. */ |
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1905 | jermar | 334 | #endif |
1903 | jermar | 335 | |
336 | 0: |
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337 | ba 0b |
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338 | nop |
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1917 | jermar | 339 | |
340 | |||
341 | .section K_DATA_START, "aw", @progbits |
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342 | |||
343 | /* |
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2049 | jermar | 344 | * Create small stack to be used by the bootstrap processor. It is going to be |
345 | * used only for a very limited period of time, but we switch to it anyway, |
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346 | * just to be sure we are properly initialized. |
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1917 | jermar | 347 | */ |
348 | |||
349 | #define INITIAL_STACK_SIZE 1024 |
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350 | |||
351 | .align STACK_ALIGNMENT |
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1978 | jermar | 352 | .space INITIAL_STACK_SIZE |
1917 | jermar | 353 | .align STACK_ALIGNMENT |
354 | temporary_boot_stack: |
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1978 | jermar | 355 | .space STACK_WINDOW_SAVE_AREA_SIZE |
356 | |||
357 | |||
358 | .data |
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359 | |||
360 | .align 8 |
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361 | .global physmem_base ! copy of the physical memory base address |
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362 | physmem_base: |
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363 | .quad 0 |
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364 | |||
365 | /* |
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2049 | jermar | 366 | * This variable is used by the fast_data_MMU_miss trap handler. In runtime, it |
367 | * is further modified to reflect the starting address of physical memory. |
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1978 | jermar | 368 | */ |
369 | .global kernel_8k_tlb_data_template |
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370 | kernel_8k_tlb_data_template: |
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2009 | jermar | 371 | #ifdef CONFIG_VIRT_IDX_DCACHE |
2049 | jermar | 372 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
373 | TTE_CV | TTE_P | TTE_W) |
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2009 | jermar | 374 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
2049 | jermar | 375 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
376 | TTE_P | TTE_W) |
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2009 | jermar | 377 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
2049 | jermar | 378 |