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3817 rimsky 1
/*
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 * Copyright (c) 2006 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup sparc64mm
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 * @{
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 */
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/** @file
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 */
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#include <arch/mm/as.h>
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#include <arch/mm/pagesize.h>
3862 rimsky 37
#include <arch/mm/tlb.h>
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#include <genarch/mm/page_ht.h>
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#include <genarch/mm/asid_fifo.h>
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#include <debug.h>
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#include <config.h>
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#ifdef CONFIG_TSB
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#include <arch/mm/tsb.h>
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#include <arch/memstr.h>
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#include <arch/asm.h>
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#include <mm/frame.h>
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#include <bitops.h>
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#include <macros.h>
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#endif /* CONFIG_TSB */
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/** Architecture dependent address space init. */
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void as_arch_init(void)
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{
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    if (config.cpu_active == 1) {
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        as_operations = &as_ht_operations;
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        asid_fifo_init();
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    }
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}
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int as_constructor_arch(as_t *as, int flags)
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{
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#ifdef CONFIG_TSB
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    /*
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     * The order must be calculated with respect to the emulated
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     * 16K page size.
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     */
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    int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
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        sizeof(tsb_entry_t)) >> FRAME_WIDTH);
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    uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
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    if (!tsb)
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        return -1;
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    as->arch.itsb = (tsb_entry_t *) tsb;
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    as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
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        sizeof(tsb_entry_t));
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    memsetb(as->arch.itsb,
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        (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
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#endif
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    return 0;
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}
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int as_destructor_arch(as_t *as)
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{
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#ifdef CONFIG_TSB
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    /*
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     * The count must be calculated with respect to the emualted 16K page
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     * size.
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     */
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    count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
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        sizeof(tsb_entry_t)) >> FRAME_WIDTH;
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    frame_free(KA2PA((uintptr_t) as->arch.itsb));
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    return cnt;
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#else
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    return 0;
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#endif
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}
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int as_create_arch(as_t *as, int flags)
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{
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#ifdef CONFIG_TSB
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    tsb_invalidate(as, 0, (count_t) -1);
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#endif
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    return 0;
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}
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/** Perform sparc64-specific tasks when an address space becomes active on the
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 * processor.
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 *
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 * Install ASID and map TSBs.
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 *
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 * @param as Address space.
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 */
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void as_install_arch(as_t *as)
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{
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    tlb_context_reg_t ctx;
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    /*
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     * Note that we don't and may not lock the address space. That's ok
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     * since we only read members that are currently read-only.
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     *
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     * Moreover, the as->asid is protected by asidlock, which is being held.
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     */
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    /*
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     * Write ASID to secondary context register. The primary context
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     * register has to be set from TL>0 so it will be filled from the
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     * secondary context register from the TL=1 code just before switch to
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     * userspace.
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     */
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    ctx.v = 0;
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    ctx.context = as->asid;
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    mmu_secondary_context_write(ctx.v);
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#ifdef CONFIG_TSB   
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    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
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    ASSERT(as->arch.itsb && as->arch.dtsb);
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    uintptr_t tsb = (uintptr_t) as->arch.itsb;
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    if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
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        /*
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         * TSBs were allocated from memory not covered
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         * by the locked 4M kernel DTLB entry. We need
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         * to map both TSBs explicitly.
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         */
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        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
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        dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
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    }
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    /*
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     * Setup TSB Base registers.
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     */
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    tsb_base_reg_t tsb_base;
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    tsb_base.value = 0;
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    tsb_base.size = TSB_SIZE;
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    tsb_base.split = 0;
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    tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
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    itsb_base_write(tsb_base.value);
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    tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
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    dtsb_base_write(tsb_base.value);
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#if defined (US3)
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    /*
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     * Clear the extension registers.
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     * In HelenOS, primary and secondary context registers contain
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     * equal values and kernel misses (context 0, ie. the nucleus context)
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     * are excluded from the TSB miss handler, so it makes no sense
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     * to have separate TSBs for primary, secondary and nucleus contexts.
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     * Clearing the extension registers will ensure that the value of the
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     * TSB Base register will be used as an address of TSB, making the code
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     * compatible with the US port.
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     */
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    itsb_primary_extension_write(0);
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    itsb_nucleus_extension_write(0);
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    dtsb_primary_extension_write(0);
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    dtsb_secondary_extension_write(0);
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    dtsb_nucleus_extension_write(0);
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#endif
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#endif
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}
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/** Perform sparc64-specific tasks when an address space is removed from the
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 * processor.
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 *
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 * Demap TSBs.
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 *
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 * @param as Address space.
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 */
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void as_deinstall_arch(as_t *as)
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{
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    /*
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     * Note that we don't and may not lock the address space. That's ok
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     * since we only read members that are currently read-only.
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     *
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     * Moreover, the as->asid is protected by asidlock, which is being held.
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     */
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#ifdef CONFIG_TSB
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    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
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    ASSERT(as->arch.itsb && as->arch.dtsb);
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    uintptr_t tsb = (uintptr_t) as->arch.itsb;
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    if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
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        /*
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         * TSBs were allocated from memory not covered
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         * by the locked 4M kernel DTLB entry. We need
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         * to demap the entry installed by as_install_arch().
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         */
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        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
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    }
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#endif
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}
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/** @}
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 */