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4638 rimsky 1
/*
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 * Copyright (c) 2005 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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/** @addtogroup sparc64interrupt
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 * @{
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 */
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/**
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 * @file
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 * @brief This file contains interrupt vector trap handler.
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 */
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#ifndef KERN_sparc64_TRAP_SUN4U_INTERRUPT_H_
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#define KERN_sparc64_TRAP_SUN4U_INTERRUPT_H_
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#include <arch/trap/trap_table.h>
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#include <arch/stack.h>
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/* Interrupt ASI registers. */
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#define ASI_INTR_W          0x77
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#define ASI_INTR_DISPATCH_STATUS    0x48
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#define ASI_INTR_R          0x7f
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#define ASI_INTR_RECEIVE        0x49
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/* VA's used with ASI_INTR_W register. */
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#if defined (US)
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#define ASI_UDB_INTR_W_DATA_0   0x40
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#define ASI_UDB_INTR_W_DATA_1   0x50
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#define ASI_UDB_INTR_W_DATA_2   0x60
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#elif defined (US3)
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#define VA_INTR_W_DATA_0    0x40
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#define VA_INTR_W_DATA_1    0x48
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#define VA_INTR_W_DATA_2    0x50
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#define VA_INTR_W_DATA_3    0x58
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#define VA_INTR_W_DATA_4    0x60
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#define VA_INTR_W_DATA_5    0x68
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#define VA_INTR_W_DATA_6    0x80
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#define VA_INTR_W_DATA_7    0x88
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#endif
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#define VA_INTR_W_DISPATCH  0x70
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/* VA's used with ASI_INTR_R register. */
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#if defined(US)
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#define ASI_UDB_INTR_R_DATA_0   0x40
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#define ASI_UDB_INTR_R_DATA_1   0x50
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#define ASI_UDB_INTR_R_DATA_2   0x60
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#elif defined (US3)
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#define VA_INTR_R_DATA_0    0x40
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#define VA_INTR_R_DATA_1    0x48
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#define VA_INTR_R_DATA_2    0x50
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#define VA_INTR_R_DATA_3    0x58
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#define VA_INTR_R_DATA_4    0x60
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#define VA_INTR_R_DATA_5    0x68
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#define VA_INTR_R_DATA_6    0x80
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#define VA_INTR_R_DATA_7    0x88
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#endif
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/* Shifts in the Interrupt Vector Dispatch virtual address. */
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#define INTR_VEC_DISPATCH_MID_SHIFT 14
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/* Bits in the Interrupt Dispatch Status register. */
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#define INTR_DISPATCH_STATUS_NACK   0x2
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#define INTR_DISPATCH_STATUS_BUSY   0x1
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#define TT_INTERRUPT_VECTOR_TRAP        0x60
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#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE  TRAP_TABLE_ENTRY_SIZE
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#ifdef __ASM__
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.macro INTERRUPT_VECTOR_TRAP_HANDLER
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    PREEMPTIBLE_HANDLER interrupt
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.endm
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#endif /* __ASM__ */
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#endif
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/** @}
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 */