Go to most recent revision | Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4638 | rimsky | 1 | /* |
| 2 | * Copyright (c) 2005 Jakub Jermar |
||
| 3 | * All rights reserved. |
||
| 4 | * |
||
| 5 | * Redistribution and use in source and binary forms, with or without |
||
| 6 | * modification, are permitted provided that the following conditions |
||
| 7 | * are met: |
||
| 8 | * |
||
| 9 | * - Redistributions of source code must retain the above copyright |
||
| 10 | * notice, this list of conditions and the following disclaimer. |
||
| 11 | * - Redistributions in binary form must reproduce the above copyright |
||
| 12 | * notice, this list of conditions and the following disclaimer in the |
||
| 13 | * documentation and/or other materials provided with the distribution. |
||
| 14 | * - The name of the author may not be used to endorse or promote products |
||
| 15 | * derived from this software without specific prior written permission. |
||
| 16 | * |
||
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
| 27 | */ |
||
| 28 | |||
| 29 | /** @addtogroup sparc64interrupt |
||
| 30 | * @{ |
||
| 31 | */ |
||
| 32 | /** |
||
| 33 | * @file |
||
| 34 | * @brief This file contains interrupt vector trap handler. |
||
| 35 | */ |
||
| 36 | |||
| 37 | #ifndef KERN_sparc64_TRAP_SUN4U_INTERRUPT_H_ |
||
| 38 | #define KERN_sparc64_TRAP_SUN4U_INTERRUPT_H_ |
||
| 39 | |||
| 40 | #include <arch/trap/trap_table.h> |
||
| 41 | #include <arch/stack.h> |
||
| 42 | |||
| 43 | |||
| 44 | /* Interrupt ASI registers. */ |
||
| 45 | #define ASI_INTR_W 0x77 |
||
| 46 | #define ASI_INTR_DISPATCH_STATUS 0x48 |
||
| 47 | #define ASI_INTR_R 0x7f |
||
| 48 | #define ASI_INTR_RECEIVE 0x49 |
||
| 49 | |||
| 50 | /* VA's used with ASI_INTR_W register. */ |
||
| 51 | #if defined (US) |
||
| 52 | #define ASI_UDB_INTR_W_DATA_0 0x40 |
||
| 53 | #define ASI_UDB_INTR_W_DATA_1 0x50 |
||
| 54 | #define ASI_UDB_INTR_W_DATA_2 0x60 |
||
| 55 | #elif defined (US3) |
||
| 56 | #define VA_INTR_W_DATA_0 0x40 |
||
| 57 | #define VA_INTR_W_DATA_1 0x48 |
||
| 58 | #define VA_INTR_W_DATA_2 0x50 |
||
| 59 | #define VA_INTR_W_DATA_3 0x58 |
||
| 60 | #define VA_INTR_W_DATA_4 0x60 |
||
| 61 | #define VA_INTR_W_DATA_5 0x68 |
||
| 62 | #define VA_INTR_W_DATA_6 0x80 |
||
| 63 | #define VA_INTR_W_DATA_7 0x88 |
||
| 64 | #endif |
||
| 65 | #define VA_INTR_W_DISPATCH 0x70 |
||
| 66 | |||
| 67 | /* VA's used with ASI_INTR_R register. */ |
||
| 68 | #if defined(US) |
||
| 69 | #define ASI_UDB_INTR_R_DATA_0 0x40 |
||
| 70 | #define ASI_UDB_INTR_R_DATA_1 0x50 |
||
| 71 | #define ASI_UDB_INTR_R_DATA_2 0x60 |
||
| 72 | #elif defined (US3) |
||
| 73 | #define VA_INTR_R_DATA_0 0x40 |
||
| 74 | #define VA_INTR_R_DATA_1 0x48 |
||
| 75 | #define VA_INTR_R_DATA_2 0x50 |
||
| 76 | #define VA_INTR_R_DATA_3 0x58 |
||
| 77 | #define VA_INTR_R_DATA_4 0x60 |
||
| 78 | #define VA_INTR_R_DATA_5 0x68 |
||
| 79 | #define VA_INTR_R_DATA_6 0x80 |
||
| 80 | #define VA_INTR_R_DATA_7 0x88 |
||
| 81 | #endif |
||
| 82 | |||
| 83 | /* Shifts in the Interrupt Vector Dispatch virtual address. */ |
||
| 84 | #define INTR_VEC_DISPATCH_MID_SHIFT 14 |
||
| 85 | |||
| 86 | /* Bits in the Interrupt Dispatch Status register. */ |
||
| 87 | #define INTR_DISPATCH_STATUS_NACK 0x2 |
||
| 88 | #define INTR_DISPATCH_STATUS_BUSY 0x1 |
||
| 89 | |||
| 90 | #define TT_INTERRUPT_VECTOR_TRAP 0x60 |
||
| 91 | |||
| 92 | #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
||
| 93 | |||
| 94 | #ifdef __ASM__ |
||
| 95 | .macro INTERRUPT_VECTOR_TRAP_HANDLER |
||
| 96 | PREEMPTIBLE_HANDLER interrupt |
||
| 97 | .endm |
||
| 98 | #endif /* __ASM__ */ |
||
| 99 | |||
| 100 | |||
| 101 | #endif |
||
| 102 | |||
| 103 | /** @} |
||
| 104 | */ |