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418 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1822 | jermar | 29 | /** @addtogroup sparc64mm |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
1860 | jermar | 35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
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418 | jermar | 37 | |
3450 | rimsky | 38 | #if defined (US) |
569 | jermar | 39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
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3450 | rimsky | 41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
42 | #endif |
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569 | jermar | 43 | |
3591 | rimsky | 44 | /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ |
3450 | rimsky | 45 | #if defined (US3) |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
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47 | #endif |
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48 | |||
1823 | jermar | 49 | #define MEM_CONTEXT_KERNEL 0 |
50 | #define MEM_CONTEXT_TEMP 1 |
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51 | |||
619 | jermar | 52 | /** Page sizes. */ |
53 | #define PAGESIZE_8K 0 |
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54 | #define PAGESIZE_64K 1 |
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55 | #define PAGESIZE_512K 2 |
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56 | #define PAGESIZE_4M 3 |
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531 | jermar | 57 | |
901 | jermar | 58 | /** Bit width of the TLB-locked portion of kernel address space. */ |
59 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
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60 | |||
1823 | jermar | 61 | /* TLB Demap Operation types. */ |
62 | #define TLB_DEMAP_PAGE 0 |
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63 | #define TLB_DEMAP_CONTEXT 1 |
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3450 | rimsky | 64 | #if defined (US3) |
65 | #define TLB_DEMAP_ALL 2 |
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66 | #endif |
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1823 | jermar | 67 | |
68 | #define TLB_DEMAP_TYPE_SHIFT 6 |
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69 | |||
70 | /* TLB Demap Operation Context register encodings. */ |
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71 | #define TLB_DEMAP_PRIMARY 0 |
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72 | #define TLB_DEMAP_SECONDARY 1 |
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73 | #define TLB_DEMAP_NUCLEUS 2 |
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74 | |||
3450 | rimsky | 75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
3440 | rimsky | 76 | #if defined (US3) |
3591 | rimsky | 77 | /* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ |
78 | #define TLB_DSMALL 0 |
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79 | #define TLB_DBIG_0 2 |
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80 | #define TLB_DBIG_1 3 |
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3440 | rimsky | 81 | |
3591 | rimsky | 82 | /* I-MMU: one small (16-entry) TLB and one big TLB */ |
83 | #define TLB_ISMALL 0 |
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84 | #define TLB_IBIG 2 |
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3440 | rimsky | 85 | #endif |
86 | |||
1823 | jermar | 87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
88 | |||
89 | /* TLB Tag Access shifts */ |
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90 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
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2054 | jermar | 91 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
1823 | jermar | 92 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
93 | |||
94 | #ifndef __ASM__ |
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95 | |||
96 | #include <arch/mm/tte.h> |
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97 | #include <arch/mm/mmu.h> |
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98 | #include <arch/mm/page.h> |
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99 | #include <arch/asm.h> |
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100 | #include <arch/barrier.h> |
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101 | #include <arch/types.h> |
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3591 | rimsky | 102 | #include <arch/register.h> |
103 | #include <arch/cpu.h> |
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1823 | jermar | 104 | |
873 | jermar | 105 | union tlb_context_reg { |
1780 | jermar | 106 | uint64_t v; |
873 | jermar | 107 | struct { |
108 | unsigned long : 51; |
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109 | unsigned context : 13; /**< Context/ASID. */ |
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110 | } __attribute__ ((packed)); |
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111 | }; |
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112 | typedef union tlb_context_reg tlb_context_reg_t; |
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113 | |||
530 | jermar | 114 | /** I-/D-TLB Data In/Access Register type. */ |
115 | typedef tte_data_t tlb_data_t; |
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116 | |||
569 | jermar | 117 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
3440 | rimsky | 118 | |
119 | #if defined (US) |
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120 | |||
569 | jermar | 121 | union tlb_data_access_addr { |
1780 | jermar | 122 | uint64_t value; |
569 | jermar | 123 | struct { |
1780 | jermar | 124 | uint64_t : 55; |
569 | jermar | 125 | unsigned tlb_entry : 6; |
126 | unsigned : 3; |
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127 | } __attribute__ ((packed)); |
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128 | }; |
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3440 | rimsky | 129 | typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
130 | typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
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131 | typedef union tlb_data_access_addr itlb_data_access_addr_t; |
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132 | typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
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418 | jermar | 133 | |
3440 | rimsky | 134 | #elif defined (US3) |
135 | |||
136 | /* |
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137 | * In US3, I-MMU and D-MMU have different formats of the data |
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138 | * access register virtual address. In the corresponding |
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139 | * structures the member variable for the entry number is |
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140 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
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141 | * for the US data access register VA structure. The rationale |
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142 | * behind this is to prevent careless mistakes in the code |
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143 | * caused by setting only the entry number and not the TLB |
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144 | * number in the US3 code (when taking the code from US). |
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145 | */ |
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146 | |||
147 | union dtlb_data_access_addr { |
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148 | uint64_t value; |
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149 | struct { |
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150 | uint64_t : 45; |
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151 | unsigned : 1; |
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152 | unsigned tlb_number : 2; |
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153 | unsigned : 4; |
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154 | unsigned local_tlb_entry : 9; |
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155 | unsigned : 3; |
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156 | } __attribute__ ((packed)); |
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157 | }; |
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158 | typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
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159 | typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
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160 | |||
161 | union itlb_data_access_addr { |
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162 | uint64_t value; |
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163 | struct { |
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164 | uint64_t : 45; |
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165 | unsigned : 1; |
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166 | unsigned tlb_number : 2; |
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167 | unsigned : 6; |
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168 | unsigned local_tlb_entry : 7; |
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169 | unsigned : 3; |
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170 | } __attribute__ ((packed)); |
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171 | }; |
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172 | typedef union itlb_data_access_addr itlb_data_access_addr_t; |
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173 | typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
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174 | |||
175 | #endif |
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176 | |||
569 | jermar | 177 | /** I-/D-TLB Tag Read Register. */ |
178 | union tlb_tag_read_reg { |
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3450 | rimsky | 179 | // TODO have a look at how non-8kB pages will be treated |
1780 | jermar | 180 | uint64_t value; |
569 | jermar | 181 | struct { |
2054 | jermar | 182 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
183 | unsigned context : 13; /**< Context identifier. */ |
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569 | jermar | 184 | } __attribute__ ((packed)); |
185 | }; |
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186 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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613 | jermar | 187 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
569 | jermar | 188 | |
617 | jermar | 189 | |
190 | /** TLB Demap Operation Address. */ |
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191 | union tlb_demap_addr { |
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1780 | jermar | 192 | uint64_t value; |
617 | jermar | 193 | struct { |
1851 | jermar | 194 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
3450 | rimsky | 195 | #if defined (US) |
617 | jermar | 196 | unsigned : 6; /**< Ignored. */ |
197 | unsigned type : 1; /**< The type of demap operation. */ |
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3450 | rimsky | 198 | #elif defined (US3) |
199 | unsigned : 5; /**< Ignored. */ |
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200 | unsigned type: 2; /**< The type of demap operation. */ |
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201 | #endif |
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617 | jermar | 202 | unsigned context : 2; /**< Context register selection. */ |
203 | unsigned : 4; /**< Zero. */ |
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204 | } __attribute__ ((packed)); |
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205 | }; |
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206 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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207 | |||
873 | jermar | 208 | /** TLB Synchronous Fault Status Register. */ |
209 | union tlb_sfsr_reg { |
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1780 | jermar | 210 | uint64_t value; |
873 | jermar | 211 | struct { |
3450 | rimsky | 212 | #if defined (US) |
1851 | jermar | 213 | unsigned long : 40; /**< Implementation dependent. */ |
873 | jermar | 214 | unsigned asi : 8; /**< ASI. */ |
1851 | jermar | 215 | unsigned : 2; |
877 | jermar | 216 | unsigned ft : 7; /**< Fault type. */ |
3450 | rimsky | 217 | #elif defined (US3) |
218 | unsigned long : 39; /**< Implementation dependent. */ |
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219 | unsigned nf : 1; /**< Non-faulting load. */ |
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220 | unsigned asi : 8; /**< ASI. */ |
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221 | unsigned tm : 1; /**< I-TLB miss. */ |
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222 | unsigned : 3; /**< Reserved. */ |
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223 | unsigned ft : 5; /**< Fault type. */ |
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224 | #endif |
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873 | jermar | 225 | unsigned e : 1; /**< Side-effect bit. */ |
226 | unsigned ct : 2; /**< Context Register selection. */ |
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227 | unsigned pr : 1; /**< Privilege bit. */ |
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228 | unsigned w : 1; /**< Write bit. */ |
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229 | unsigned ow : 1; /**< Overwrite bit. */ |
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877 | jermar | 230 | unsigned fv : 1; /**< Fault Valid bit. */ |
873 | jermar | 231 | } __attribute__ ((packed)); |
232 | }; |
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233 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
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234 | |||
3591 | rimsky | 235 | #if defined (US3) |
236 | |||
237 | /* |
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238 | * Functions for determining the number of entries in TLBs. They either return |
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239 | * a constant value or a value based on the CPU autodetection. |
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240 | */ |
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241 | |||
242 | /** |
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243 | * Determine the number od entries in the DMMU's small TLB. |
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244 | */ |
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245 | static inline uint16_t tlb_dsmall_size(void) |
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246 | { |
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247 | return 16; |
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248 | } |
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249 | |||
250 | /** |
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251 | * Determine the number od entries in each DMMU's big TLB. |
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252 | */ |
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253 | static inline uint16_t tlb_dbig_size(void) |
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254 | { |
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255 | return 512; |
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256 | } |
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257 | |||
258 | /** |
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259 | * Determine the number od entries in the IMMU's small TLB. |
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260 | */ |
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261 | static inline uint16_t tlb_ismall_size(void) |
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262 | { |
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263 | return 16; |
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264 | } |
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265 | |||
266 | /** |
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267 | * Determine the number od entries in the IMMU's big TLB. |
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268 | */ |
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269 | static inline uint16_t tlb_ibig_size(void) |
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270 | { |
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271 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
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272 | return 512; |
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273 | else |
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274 | return 128; |
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275 | } |
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276 | |||
277 | #endif |
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278 | |||
873 | jermar | 279 | /** Read MMU Primary Context Register. |
280 | * |
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281 | * @return Current value of Primary Context Register. |
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282 | */ |
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1780 | jermar | 283 | static inline uint64_t mmu_primary_context_read(void) |
873 | jermar | 284 | { |
285 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
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286 | } |
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287 | |||
288 | /** Write MMU Primary Context Register. |
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289 | * |
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290 | * @param v New value of Primary Context Register. |
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291 | */ |
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1780 | jermar | 292 | static inline void mmu_primary_context_write(uint64_t v) |
873 | jermar | 293 | { |
294 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
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3145 | jermar | 295 | flush_pipeline(); |
873 | jermar | 296 | } |
297 | |||
298 | /** Read MMU Secondary Context Register. |
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299 | * |
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300 | * @return Current value of Secondary Context Register. |
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301 | */ |
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1780 | jermar | 302 | static inline uint64_t mmu_secondary_context_read(void) |
873 | jermar | 303 | { |
304 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
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305 | } |
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306 | |||
307 | /** Write MMU Primary Context Register. |
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308 | * |
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309 | * @param v New value of Primary Context Register. |
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310 | */ |
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1780 | jermar | 311 | static inline void mmu_secondary_context_write(uint64_t v) |
873 | jermar | 312 | { |
1864 | jermar | 313 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
3145 | jermar | 314 | flush_pipeline(); |
873 | jermar | 315 | } |
316 | |||
3440 | rimsky | 317 | #if defined (US) |
318 | |||
569 | jermar | 319 | /** Read IMMU TLB Data Access Register. |
320 | * |
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321 | * @param entry TLB Entry index. |
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322 | * |
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323 | * @return Current value of specified IMMU TLB Data Access Register. |
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324 | */ |
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1780 | jermar | 325 | static inline uint64_t itlb_data_access_read(index_t entry) |
569 | jermar | 326 | { |
3440 | rimsky | 327 | itlb_data_access_addr_t reg; |
569 | jermar | 328 | |
329 | reg.value = 0; |
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330 | reg.tlb_entry = entry; |
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331 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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332 | } |
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333 | |||
617 | jermar | 334 | /** Write IMMU TLB Data Access Register. |
335 | * |
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336 | * @param entry TLB Entry index. |
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337 | * @param value Value to be written. |
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338 | */ |
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1780 | jermar | 339 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 340 | { |
3440 | rimsky | 341 | itlb_data_access_addr_t reg; |
617 | jermar | 342 | |
343 | reg.value = 0; |
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344 | reg.tlb_entry = entry; |
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345 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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3145 | jermar | 346 | flush_pipeline(); |
617 | jermar | 347 | } |
348 | |||
569 | jermar | 349 | /** Read DMMU TLB Data Access Register. |
350 | * |
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351 | * @param entry TLB Entry index. |
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352 | * |
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353 | * @return Current value of specified DMMU TLB Data Access Register. |
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354 | */ |
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1780 | jermar | 355 | static inline uint64_t dtlb_data_access_read(index_t entry) |
569 | jermar | 356 | { |
3440 | rimsky | 357 | dtlb_data_access_addr_t reg; |
569 | jermar | 358 | |
359 | reg.value = 0; |
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360 | reg.tlb_entry = entry; |
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361 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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362 | } |
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363 | |||
617 | jermar | 364 | /** Write DMMU TLB Data Access Register. |
365 | * |
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366 | * @param entry TLB Entry index. |
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367 | * @param value Value to be written. |
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368 | */ |
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1780 | jermar | 369 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 370 | { |
3440 | rimsky | 371 | dtlb_data_access_addr_t reg; |
617 | jermar | 372 | |
373 | reg.value = 0; |
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374 | reg.tlb_entry = entry; |
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375 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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1822 | jermar | 376 | membar(); |
617 | jermar | 377 | } |
378 | |||
569 | jermar | 379 | /** Read IMMU TLB Tag Read Register. |
380 | * |
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381 | * @param entry TLB Entry index. |
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382 | * |
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383 | * @return Current value of specified IMMU TLB Tag Read Register. |
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384 | */ |
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1780 | jermar | 385 | static inline uint64_t itlb_tag_read_read(index_t entry) |
569 | jermar | 386 | { |
3440 | rimsky | 387 | itlb_tag_read_addr_t tag; |
569 | jermar | 388 | |
389 | tag.value = 0; |
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390 | tag.tlb_entry = entry; |
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391 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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392 | } |
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393 | |||
394 | /** Read DMMU TLB Tag Read Register. |
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395 | * |
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396 | * @param entry TLB Entry index. |
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397 | * |
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398 | * @return Current value of specified DMMU TLB Tag Read Register. |
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399 | */ |
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1780 | jermar | 400 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
569 | jermar | 401 | { |
3440 | rimsky | 402 | dtlb_tag_read_addr_t tag; |
569 | jermar | 403 | |
404 | tag.value = 0; |
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405 | tag.tlb_entry = entry; |
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406 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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407 | } |
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408 | |||
3440 | rimsky | 409 | #elif defined (US3) |
410 | |||
411 | |||
412 | /** Read IMMU TLB Data Access Register. |
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413 | * |
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3591 | rimsky | 414 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
3440 | rimsky | 415 | * @param entry TLB Entry index. |
416 | * |
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417 | * @return Current value of specified IMMU TLB Data Access Register. |
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418 | */ |
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419 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
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420 | { |
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421 | itlb_data_access_addr_t reg; |
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422 | |||
423 | reg.value = 0; |
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424 | reg.tlb_number = tlb; |
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425 | reg.local_tlb_entry = entry; |
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426 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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427 | } |
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428 | |||
429 | /** Write IMMU TLB Data Access Register. |
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3591 | rimsky | 430 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
3440 | rimsky | 431 | * @param entry TLB Entry index. |
432 | * @param value Value to be written. |
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433 | */ |
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434 | static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value) |
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435 | { |
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436 | itlb_data_access_addr_t reg; |
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437 | |||
438 | reg.value = 0; |
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439 | reg.tlb_number = tlb; |
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440 | reg.local_tlb_entry = entry; |
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441 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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442 | flush_pipeline(); |
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443 | } |
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444 | |||
445 | /** Read DMMU TLB Data Access Register. |
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446 | * |
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3591 | rimsky | 447 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
3440 | rimsky | 448 | * @param entry TLB Entry index. |
449 | * |
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450 | * @return Current value of specified DMMU TLB Data Access Register. |
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451 | */ |
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452 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
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453 | { |
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454 | dtlb_data_access_addr_t reg; |
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455 | |||
456 | reg.value = 0; |
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457 | reg.tlb_number = tlb; |
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458 | reg.local_tlb_entry = entry; |
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459 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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460 | } |
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461 | |||
462 | /** Write DMMU TLB Data Access Register. |
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463 | * |
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3591 | rimsky | 464 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
3440 | rimsky | 465 | * @param entry TLB Entry index. |
466 | * @param value Value to be written. |
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467 | */ |
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468 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
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469 | { |
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470 | dtlb_data_access_addr_t reg; |
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471 | |||
472 | reg.value = 0; |
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473 | reg.tlb_number = tlb; |
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474 | reg.local_tlb_entry = entry; |
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475 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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476 | membar(); |
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477 | } |
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478 | |||
479 | /** Read IMMU TLB Tag Read Register. |
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480 | * |
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3591 | rimsky | 481 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
3440 | rimsky | 482 | * @param entry TLB Entry index. |
483 | * |
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484 | * @return Current value of specified IMMU TLB Tag Read Register. |
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485 | */ |
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486 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
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487 | { |
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488 | itlb_tag_read_addr_t tag; |
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489 | |||
490 | tag.value = 0; |
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491 | tag.tlb_number = tlb; |
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492 | tag.local_tlb_entry = entry; |
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493 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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494 | } |
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495 | |||
496 | /** Read DMMU TLB Tag Read Register. |
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497 | * |
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3591 | rimsky | 498 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
3440 | rimsky | 499 | * @param entry TLB Entry index. |
500 | * |
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501 | * @return Current value of specified DMMU TLB Tag Read Register. |
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502 | */ |
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503 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
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504 | { |
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505 | dtlb_tag_read_addr_t tag; |
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506 | |||
507 | tag.value = 0; |
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508 | tag.tlb_number = tlb; |
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509 | tag.local_tlb_entry = entry; |
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510 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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511 | } |
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512 | |||
513 | #endif |
||
514 | |||
515 | |||
613 | jermar | 516 | /** Write IMMU TLB Tag Access Register. |
517 | * |
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518 | * @param v Value to be written. |
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519 | */ |
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1780 | jermar | 520 | static inline void itlb_tag_access_write(uint64_t v) |
613 | jermar | 521 | { |
522 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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3145 | jermar | 523 | flush_pipeline(); |
613 | jermar | 524 | } |
525 | |||
877 | jermar | 526 | /** Read IMMU TLB Tag Access Register. |
527 | * |
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528 | * @return Current value of IMMU TLB Tag Access Register. |
||
529 | */ |
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1780 | jermar | 530 | static inline uint64_t itlb_tag_access_read(void) |
877 | jermar | 531 | { |
532 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
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533 | } |
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534 | |||
613 | jermar | 535 | /** Write DMMU TLB Tag Access Register. |
536 | * |
||
537 | * @param v Value to be written. |
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538 | */ |
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1780 | jermar | 539 | static inline void dtlb_tag_access_write(uint64_t v) |
613 | jermar | 540 | { |
541 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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1822 | jermar | 542 | membar(); |
613 | jermar | 543 | } |
544 | |||
877 | jermar | 545 | /** Read DMMU TLB Tag Access Register. |
546 | * |
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547 | * @return Current value of DMMU TLB Tag Access Register. |
||
548 | */ |
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1780 | jermar | 549 | static inline uint64_t dtlb_tag_access_read(void) |
877 | jermar | 550 | { |
551 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
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552 | } |
||
553 | |||
554 | |||
613 | jermar | 555 | /** Write IMMU TLB Data in Register. |
556 | * |
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557 | * @param v Value to be written. |
||
558 | */ |
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1780 | jermar | 559 | static inline void itlb_data_in_write(uint64_t v) |
613 | jermar | 560 | { |
561 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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3145 | jermar | 562 | flush_pipeline(); |
613 | jermar | 563 | } |
564 | |||
565 | /** Write DMMU TLB Data in Register. |
||
566 | * |
||
567 | * @param v Value to be written. |
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568 | */ |
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1780 | jermar | 569 | static inline void dtlb_data_in_write(uint64_t v) |
613 | jermar | 570 | { |
571 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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1822 | jermar | 572 | membar(); |
613 | jermar | 573 | } |
574 | |||
873 | jermar | 575 | /** Read ITLB Synchronous Fault Status Register. |
576 | * |
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577 | * @return Current content of I-SFSR register. |
||
578 | */ |
||
1780 | jermar | 579 | static inline uint64_t itlb_sfsr_read(void) |
873 | jermar | 580 | { |
581 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
||
582 | } |
||
583 | |||
584 | /** Write ITLB Synchronous Fault Status Register. |
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585 | * |
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586 | * @param v New value of I-SFSR register. |
||
587 | */ |
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1780 | jermar | 588 | static inline void itlb_sfsr_write(uint64_t v) |
873 | jermar | 589 | { |
590 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
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3145 | jermar | 591 | flush_pipeline(); |
873 | jermar | 592 | } |
593 | |||
594 | /** Read DTLB Synchronous Fault Status Register. |
||
595 | * |
||
596 | * @return Current content of D-SFSR register. |
||
597 | */ |
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1780 | jermar | 598 | static inline uint64_t dtlb_sfsr_read(void) |
873 | jermar | 599 | { |
600 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
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601 | } |
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602 | |||
603 | /** Write DTLB Synchronous Fault Status Register. |
||
604 | * |
||
605 | * @param v New value of D-SFSR register. |
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606 | */ |
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1780 | jermar | 607 | static inline void dtlb_sfsr_write(uint64_t v) |
873 | jermar | 608 | { |
609 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
||
1822 | jermar | 610 | membar(); |
873 | jermar | 611 | } |
612 | |||
613 | /** Read DTLB Synchronous Fault Address Register. |
||
614 | * |
||
615 | * @return Current content of D-SFAR register. |
||
616 | */ |
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1780 | jermar | 617 | static inline uint64_t dtlb_sfar_read(void) |
873 | jermar | 618 | { |
619 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
||
620 | } |
||
621 | |||
617 | jermar | 622 | /** Perform IMMU TLB Demap Operation. |
623 | * |
||
3450 | rimsky | 624 | * @param type |
625 | * Selects between context and page demap |
||
3607 | rimsky | 626 | * (and entire MMU demap on US3). |
2054 | jermar | 627 | * @param context_encoding Specifies which Context register has Context ID for |
628 | * demap. |
||
617 | jermar | 629 | * @param page Address which is on the page to be demapped. |
630 | */ |
||
1780 | jermar | 631 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 632 | { |
633 | tlb_demap_addr_t da; |
||
634 | page_address_t pg; |
||
635 | |||
636 | da.value = 0; |
||
637 | pg.address = page; |
||
638 | |||
639 | da.type = type; |
||
640 | da.context = context_encoding; |
||
641 | da.vpn = pg.vpn; |
||
642 | |||
2054 | jermar | 643 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
644 | * address within the |
||
645 | * ASI */ |
||
3145 | jermar | 646 | flush_pipeline(); |
617 | jermar | 647 | } |
648 | |||
649 | /** Perform DMMU TLB Demap Operation. |
||
650 | * |
||
3450 | rimsky | 651 | * @param type |
652 | * Selects between context and page demap |
||
3607 | rimsky | 653 | * (and entire MMU demap on US3). |
2054 | jermar | 654 | * @param context_encoding Specifies which Context register has Context ID for |
655 | * demap. |
||
617 | jermar | 656 | * @param page Address which is on the page to be demapped. |
657 | */ |
||
1780 | jermar | 658 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 659 | { |
660 | tlb_demap_addr_t da; |
||
661 | page_address_t pg; |
||
662 | |||
663 | da.value = 0; |
||
664 | pg.address = page; |
||
665 | |||
666 | da.type = type; |
||
667 | da.context = context_encoding; |
||
668 | da.vpn = pg.vpn; |
||
669 | |||
2054 | jermar | 670 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
671 | * address within the |
||
672 | * ASI */ |
||
1822 | jermar | 673 | membar(); |
617 | jermar | 674 | } |
675 | |||
2231 | jermar | 676 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
677 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
||
678 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
||
863 | jermar | 679 | |
1780 | jermar | 680 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
897 | jermar | 681 | |
1946 | jermar | 682 | extern void dump_sfsr_and_sfar(void); |
683 | |||
1823 | jermar | 684 | #endif /* !def __ASM__ */ |
685 | |||
418 | jermar | 686 | #endif |
1702 | cejka | 687 | |
1822 | jermar | 688 | /** @} |
3493 | rimsky | 689 | */ |