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418 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1822 | jermar | 29 | /** @addtogroup sparc64mm |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
1860 | jermar | 35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
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418 | jermar | 37 | |
3450 | rimsky | 38 | #if defined (US) |
569 | jermar | 39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
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3450 | rimsky | 41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
42 | #endif |
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569 | jermar | 43 | |
3493 | rimsky | 44 | /** DT16 is the only of the three DMMUs that can hold locked entries. */ |
3450 | rimsky | 45 | #if defined (US3) |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
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47 | #endif |
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48 | |||
1823 | jermar | 49 | #define MEM_CONTEXT_KERNEL 0 |
50 | #define MEM_CONTEXT_TEMP 1 |
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51 | |||
619 | jermar | 52 | /** Page sizes. */ |
53 | #define PAGESIZE_8K 0 |
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54 | #define PAGESIZE_64K 1 |
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55 | #define PAGESIZE_512K 2 |
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56 | #define PAGESIZE_4M 3 |
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531 | jermar | 57 | |
901 | jermar | 58 | /** Bit width of the TLB-locked portion of kernel address space. */ |
59 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
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60 | |||
1823 | jermar | 61 | /* TLB Demap Operation types. */ |
62 | #define TLB_DEMAP_PAGE 0 |
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63 | #define TLB_DEMAP_CONTEXT 1 |
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3450 | rimsky | 64 | #if defined (US3) |
65 | #define TLB_DEMAP_ALL 2 |
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66 | #endif |
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1823 | jermar | 67 | |
68 | #define TLB_DEMAP_TYPE_SHIFT 6 |
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69 | |||
70 | /* TLB Demap Operation Context register encodings. */ |
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71 | #define TLB_DEMAP_PRIMARY 0 |
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72 | #define TLB_DEMAP_SECONDARY 1 |
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73 | #define TLB_DEMAP_NUCLEUS 2 |
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74 | |||
3450 | rimsky | 75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
3440 | rimsky | 76 | #if defined (US3) |
3450 | rimsky | 77 | /* D-MMU: one 16-entry TLB and two 512-entry TLBs */ |
78 | #define TLB_DT16 0 |
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79 | #define TLB_DT512_0 2 |
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80 | #define TLB_DT512_1 3 |
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3440 | rimsky | 81 | |
3450 | rimsky | 82 | /* I-MMU: one 16-entry TLB and one 128-entry TLB */ |
83 | #define TLB_IT16 0 |
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84 | #define TLB_IT128 2 |
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3440 | rimsky | 85 | #endif |
86 | |||
1823 | jermar | 87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
88 | |||
89 | /* TLB Tag Access shifts */ |
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90 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
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2054 | jermar | 91 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
1823 | jermar | 92 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
93 | |||
94 | #ifndef __ASM__ |
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95 | |||
96 | #include <arch/mm/tte.h> |
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97 | #include <arch/mm/mmu.h> |
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98 | #include <arch/mm/page.h> |
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99 | #include <arch/asm.h> |
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100 | #include <arch/barrier.h> |
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101 | #include <arch/types.h> |
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102 | |||
873 | jermar | 103 | union tlb_context_reg { |
1780 | jermar | 104 | uint64_t v; |
873 | jermar | 105 | struct { |
106 | unsigned long : 51; |
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107 | unsigned context : 13; /**< Context/ASID. */ |
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108 | } __attribute__ ((packed)); |
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109 | }; |
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110 | typedef union tlb_context_reg tlb_context_reg_t; |
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111 | |||
530 | jermar | 112 | /** I-/D-TLB Data In/Access Register type. */ |
113 | typedef tte_data_t tlb_data_t; |
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114 | |||
569 | jermar | 115 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
3440 | rimsky | 116 | |
117 | #if defined (US) |
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118 | |||
569 | jermar | 119 | union tlb_data_access_addr { |
1780 | jermar | 120 | uint64_t value; |
569 | jermar | 121 | struct { |
1780 | jermar | 122 | uint64_t : 55; |
569 | jermar | 123 | unsigned tlb_entry : 6; |
124 | unsigned : 3; |
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125 | } __attribute__ ((packed)); |
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126 | }; |
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3440 | rimsky | 127 | typedef union tlb_data_access_addr dtlb_data_access_addr_t; |
128 | typedef union tlb_data_access_addr dtlb_tag_read_addr_t; |
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129 | typedef union tlb_data_access_addr itlb_data_access_addr_t; |
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130 | typedef union tlb_data_access_addr itlb_tag_read_addr_t; |
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418 | jermar | 131 | |
3440 | rimsky | 132 | #elif defined (US3) |
133 | |||
134 | /* |
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135 | * In US3, I-MMU and D-MMU have different formats of the data |
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136 | * access register virtual address. In the corresponding |
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137 | * structures the member variable for the entry number is |
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138 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
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139 | * for the US data access register VA structure. The rationale |
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140 | * behind this is to prevent careless mistakes in the code |
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141 | * caused by setting only the entry number and not the TLB |
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142 | * number in the US3 code (when taking the code from US). |
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143 | */ |
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144 | |||
145 | union dtlb_data_access_addr { |
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146 | uint64_t value; |
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147 | struct { |
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148 | uint64_t : 45; |
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149 | unsigned : 1; |
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150 | unsigned tlb_number : 2; |
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151 | unsigned : 4; |
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152 | unsigned local_tlb_entry : 9; |
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153 | unsigned : 3; |
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154 | } __attribute__ ((packed)); |
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155 | }; |
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156 | typedef union dtlb_data_access_addr dtlb_data_access_addr_t; |
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157 | typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; |
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158 | |||
159 | union itlb_data_access_addr { |
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160 | uint64_t value; |
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161 | struct { |
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162 | uint64_t : 45; |
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163 | unsigned : 1; |
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164 | unsigned tlb_number : 2; |
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165 | unsigned : 6; |
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166 | unsigned local_tlb_entry : 7; |
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167 | unsigned : 3; |
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168 | } __attribute__ ((packed)); |
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169 | }; |
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170 | typedef union itlb_data_access_addr itlb_data_access_addr_t; |
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171 | typedef union itlb_data_access_addr itlb_tag_read_addr_t; |
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172 | |||
173 | #endif |
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174 | |||
569 | jermar | 175 | /** I-/D-TLB Tag Read Register. */ |
176 | union tlb_tag_read_reg { |
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3450 | rimsky | 177 | // TODO have a look at how non-8kB pages will be treated |
1780 | jermar | 178 | uint64_t value; |
569 | jermar | 179 | struct { |
2054 | jermar | 180 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
181 | unsigned context : 13; /**< Context identifier. */ |
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569 | jermar | 182 | } __attribute__ ((packed)); |
183 | }; |
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184 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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613 | jermar | 185 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
569 | jermar | 186 | |
617 | jermar | 187 | |
188 | /** TLB Demap Operation Address. */ |
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189 | union tlb_demap_addr { |
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1780 | jermar | 190 | uint64_t value; |
617 | jermar | 191 | struct { |
1851 | jermar | 192 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
3450 | rimsky | 193 | #if defined (US) |
617 | jermar | 194 | unsigned : 6; /**< Ignored. */ |
195 | unsigned type : 1; /**< The type of demap operation. */ |
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3450 | rimsky | 196 | #elif defined (US3) |
197 | unsigned : 5; /**< Ignored. */ |
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198 | unsigned type: 2; /**< The type of demap operation. */ |
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199 | #endif |
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617 | jermar | 200 | unsigned context : 2; /**< Context register selection. */ |
201 | unsigned : 4; /**< Zero. */ |
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202 | } __attribute__ ((packed)); |
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203 | }; |
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204 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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205 | |||
873 | jermar | 206 | /** TLB Synchronous Fault Status Register. */ |
207 | union tlb_sfsr_reg { |
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1780 | jermar | 208 | uint64_t value; |
873 | jermar | 209 | struct { |
3450 | rimsky | 210 | #if defined (US) |
1851 | jermar | 211 | unsigned long : 40; /**< Implementation dependent. */ |
873 | jermar | 212 | unsigned asi : 8; /**< ASI. */ |
1851 | jermar | 213 | unsigned : 2; |
877 | jermar | 214 | unsigned ft : 7; /**< Fault type. */ |
3450 | rimsky | 215 | #elif defined (US3) |
216 | unsigned long : 39; /**< Implementation dependent. */ |
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217 | unsigned nf : 1; /**< Non-faulting load. */ |
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218 | unsigned asi : 8; /**< ASI. */ |
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219 | unsigned tm : 1; /**< I-TLB miss. */ |
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220 | unsigned : 3; /**< Reserved. */ |
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221 | unsigned ft : 5; /**< Fault type. */ |
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222 | #endif |
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873 | jermar | 223 | unsigned e : 1; /**< Side-effect bit. */ |
224 | unsigned ct : 2; /**< Context Register selection. */ |
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225 | unsigned pr : 1; /**< Privilege bit. */ |
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226 | unsigned w : 1; /**< Write bit. */ |
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227 | unsigned ow : 1; /**< Overwrite bit. */ |
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877 | jermar | 228 | unsigned fv : 1; /**< Fault Valid bit. */ |
873 | jermar | 229 | } __attribute__ ((packed)); |
230 | }; |
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231 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
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232 | |||
233 | /** Read MMU Primary Context Register. |
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234 | * |
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235 | * @return Current value of Primary Context Register. |
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236 | */ |
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1780 | jermar | 237 | static inline uint64_t mmu_primary_context_read(void) |
873 | jermar | 238 | { |
239 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
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240 | } |
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241 | |||
242 | /** Write MMU Primary Context Register. |
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243 | * |
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244 | * @param v New value of Primary Context Register. |
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245 | */ |
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1780 | jermar | 246 | static inline void mmu_primary_context_write(uint64_t v) |
873 | jermar | 247 | { |
248 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
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3145 | jermar | 249 | flush_pipeline(); |
873 | jermar | 250 | } |
251 | |||
252 | /** Read MMU Secondary Context Register. |
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253 | * |
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254 | * @return Current value of Secondary Context Register. |
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255 | */ |
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1780 | jermar | 256 | static inline uint64_t mmu_secondary_context_read(void) |
873 | jermar | 257 | { |
258 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
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259 | } |
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260 | |||
261 | /** Write MMU Primary Context Register. |
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262 | * |
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263 | * @param v New value of Primary Context Register. |
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264 | */ |
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1780 | jermar | 265 | static inline void mmu_secondary_context_write(uint64_t v) |
873 | jermar | 266 | { |
1864 | jermar | 267 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
3145 | jermar | 268 | flush_pipeline(); |
873 | jermar | 269 | } |
270 | |||
3440 | rimsky | 271 | #if defined (US) |
272 | |||
569 | jermar | 273 | /** Read IMMU TLB Data Access Register. |
274 | * |
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275 | * @param entry TLB Entry index. |
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276 | * |
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277 | * @return Current value of specified IMMU TLB Data Access Register. |
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278 | */ |
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1780 | jermar | 279 | static inline uint64_t itlb_data_access_read(index_t entry) |
569 | jermar | 280 | { |
3440 | rimsky | 281 | itlb_data_access_addr_t reg; |
569 | jermar | 282 | |
283 | reg.value = 0; |
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284 | reg.tlb_entry = entry; |
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285 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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286 | } |
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287 | |||
617 | jermar | 288 | /** Write IMMU TLB Data Access Register. |
289 | * |
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290 | * @param entry TLB Entry index. |
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291 | * @param value Value to be written. |
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292 | */ |
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1780 | jermar | 293 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 294 | { |
3440 | rimsky | 295 | itlb_data_access_addr_t reg; |
617 | jermar | 296 | |
297 | reg.value = 0; |
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298 | reg.tlb_entry = entry; |
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299 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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3145 | jermar | 300 | flush_pipeline(); |
617 | jermar | 301 | } |
302 | |||
569 | jermar | 303 | /** Read DMMU TLB Data Access Register. |
304 | * |
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305 | * @param entry TLB Entry index. |
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306 | * |
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307 | * @return Current value of specified DMMU TLB Data Access Register. |
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308 | */ |
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1780 | jermar | 309 | static inline uint64_t dtlb_data_access_read(index_t entry) |
569 | jermar | 310 | { |
3440 | rimsky | 311 | dtlb_data_access_addr_t reg; |
569 | jermar | 312 | |
313 | reg.value = 0; |
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314 | reg.tlb_entry = entry; |
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315 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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316 | } |
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317 | |||
617 | jermar | 318 | /** Write DMMU TLB Data Access Register. |
319 | * |
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320 | * @param entry TLB Entry index. |
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321 | * @param value Value to be written. |
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322 | */ |
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1780 | jermar | 323 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 324 | { |
3440 | rimsky | 325 | dtlb_data_access_addr_t reg; |
617 | jermar | 326 | |
327 | reg.value = 0; |
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328 | reg.tlb_entry = entry; |
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329 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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1822 | jermar | 330 | membar(); |
617 | jermar | 331 | } |
332 | |||
569 | jermar | 333 | /** Read IMMU TLB Tag Read Register. |
334 | * |
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335 | * @param entry TLB Entry index. |
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336 | * |
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337 | * @return Current value of specified IMMU TLB Tag Read Register. |
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338 | */ |
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1780 | jermar | 339 | static inline uint64_t itlb_tag_read_read(index_t entry) |
569 | jermar | 340 | { |
3440 | rimsky | 341 | itlb_tag_read_addr_t tag; |
569 | jermar | 342 | |
343 | tag.value = 0; |
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344 | tag.tlb_entry = entry; |
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345 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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346 | } |
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347 | |||
348 | /** Read DMMU TLB Tag Read Register. |
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349 | * |
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350 | * @param entry TLB Entry index. |
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351 | * |
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352 | * @return Current value of specified DMMU TLB Tag Read Register. |
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353 | */ |
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1780 | jermar | 354 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
569 | jermar | 355 | { |
3440 | rimsky | 356 | dtlb_tag_read_addr_t tag; |
569 | jermar | 357 | |
358 | tag.value = 0; |
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359 | tag.tlb_entry = entry; |
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360 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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361 | } |
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362 | |||
3440 | rimsky | 363 | #elif defined (US3) |
364 | |||
365 | |||
366 | /** Read IMMU TLB Data Access Register. |
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367 | * |
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368 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
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369 | * @param entry TLB Entry index. |
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370 | * |
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371 | * @return Current value of specified IMMU TLB Data Access Register. |
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372 | */ |
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373 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
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374 | { |
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375 | itlb_data_access_addr_t reg; |
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376 | |||
377 | reg.value = 0; |
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378 | reg.tlb_number = tlb; |
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379 | reg.local_tlb_entry = entry; |
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380 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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381 | } |
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382 | |||
383 | /** Write IMMU TLB Data Access Register. |
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384 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
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385 | * @param entry TLB Entry index. |
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386 | * @param value Value to be written. |
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387 | */ |
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388 | static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value) |
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389 | { |
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390 | itlb_data_access_addr_t reg; |
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391 | |||
392 | reg.value = 0; |
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393 | reg.tlb_number = tlb; |
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394 | reg.local_tlb_entry = entry; |
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395 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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396 | flush_pipeline(); |
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397 | } |
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398 | |||
399 | /** Read DMMU TLB Data Access Register. |
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400 | * |
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3450 | rimsky | 401 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
3440 | rimsky | 402 | * @param entry TLB Entry index. |
403 | * |
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404 | * @return Current value of specified DMMU TLB Data Access Register. |
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405 | */ |
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406 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
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407 | { |
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408 | dtlb_data_access_addr_t reg; |
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409 | |||
410 | reg.value = 0; |
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411 | reg.tlb_number = tlb; |
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412 | reg.local_tlb_entry = entry; |
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413 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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414 | } |
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415 | |||
416 | /** Write DMMU TLB Data Access Register. |
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417 | * |
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3450 | rimsky | 418 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
3440 | rimsky | 419 | * @param entry TLB Entry index. |
420 | * @param value Value to be written. |
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421 | */ |
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422 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
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423 | { |
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424 | dtlb_data_access_addr_t reg; |
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425 | |||
426 | reg.value = 0; |
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427 | reg.tlb_number = tlb; |
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428 | reg.local_tlb_entry = entry; |
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429 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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430 | membar(); |
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431 | } |
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432 | |||
433 | /** Read IMMU TLB Tag Read Register. |
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434 | * |
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435 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
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436 | * @param entry TLB Entry index. |
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437 | * |
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438 | * @return Current value of specified IMMU TLB Tag Read Register. |
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439 | */ |
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440 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
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441 | { |
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442 | itlb_tag_read_addr_t tag; |
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443 | |||
444 | tag.value = 0; |
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445 | tag.tlb_number = tlb; |
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446 | tag.local_tlb_entry = entry; |
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447 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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448 | } |
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449 | |||
450 | /** Read DMMU TLB Tag Read Register. |
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451 | * |
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3450 | rimsky | 452 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
3440 | rimsky | 453 | * @param entry TLB Entry index. |
454 | * |
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455 | * @return Current value of specified DMMU TLB Tag Read Register. |
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456 | */ |
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457 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
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458 | { |
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459 | dtlb_tag_read_addr_t tag; |
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460 | |||
461 | tag.value = 0; |
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462 | tag.tlb_number = tlb; |
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463 | tag.local_tlb_entry = entry; |
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464 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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465 | } |
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466 | |||
467 | #endif |
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468 | |||
469 | |||
613 | jermar | 470 | /** Write IMMU TLB Tag Access Register. |
471 | * |
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472 | * @param v Value to be written. |
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473 | */ |
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1780 | jermar | 474 | static inline void itlb_tag_access_write(uint64_t v) |
613 | jermar | 475 | { |
476 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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3145 | jermar | 477 | flush_pipeline(); |
613 | jermar | 478 | } |
479 | |||
877 | jermar | 480 | /** Read IMMU TLB Tag Access Register. |
481 | * |
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482 | * @return Current value of IMMU TLB Tag Access Register. |
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483 | */ |
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1780 | jermar | 484 | static inline uint64_t itlb_tag_access_read(void) |
877 | jermar | 485 | { |
486 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
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487 | } |
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488 | |||
613 | jermar | 489 | /** Write DMMU TLB Tag Access Register. |
490 | * |
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491 | * @param v Value to be written. |
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492 | */ |
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1780 | jermar | 493 | static inline void dtlb_tag_access_write(uint64_t v) |
613 | jermar | 494 | { |
495 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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1822 | jermar | 496 | membar(); |
613 | jermar | 497 | } |
498 | |||
877 | jermar | 499 | /** Read DMMU TLB Tag Access Register. |
500 | * |
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501 | * @return Current value of DMMU TLB Tag Access Register. |
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502 | */ |
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1780 | jermar | 503 | static inline uint64_t dtlb_tag_access_read(void) |
877 | jermar | 504 | { |
505 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
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506 | } |
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507 | |||
508 | |||
613 | jermar | 509 | /** Write IMMU TLB Data in Register. |
510 | * |
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511 | * @param v Value to be written. |
||
512 | */ |
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1780 | jermar | 513 | static inline void itlb_data_in_write(uint64_t v) |
613 | jermar | 514 | { |
515 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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3145 | jermar | 516 | flush_pipeline(); |
613 | jermar | 517 | } |
518 | |||
519 | /** Write DMMU TLB Data in Register. |
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520 | * |
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521 | * @param v Value to be written. |
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522 | */ |
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1780 | jermar | 523 | static inline void dtlb_data_in_write(uint64_t v) |
613 | jermar | 524 | { |
525 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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1822 | jermar | 526 | membar(); |
613 | jermar | 527 | } |
528 | |||
873 | jermar | 529 | /** Read ITLB Synchronous Fault Status Register. |
530 | * |
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531 | * @return Current content of I-SFSR register. |
||
532 | */ |
||
1780 | jermar | 533 | static inline uint64_t itlb_sfsr_read(void) |
873 | jermar | 534 | { |
535 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
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536 | } |
||
537 | |||
538 | /** Write ITLB Synchronous Fault Status Register. |
||
539 | * |
||
540 | * @param v New value of I-SFSR register. |
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541 | */ |
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1780 | jermar | 542 | static inline void itlb_sfsr_write(uint64_t v) |
873 | jermar | 543 | { |
544 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
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3145 | jermar | 545 | flush_pipeline(); |
873 | jermar | 546 | } |
547 | |||
548 | /** Read DTLB Synchronous Fault Status Register. |
||
549 | * |
||
550 | * @return Current content of D-SFSR register. |
||
551 | */ |
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1780 | jermar | 552 | static inline uint64_t dtlb_sfsr_read(void) |
873 | jermar | 553 | { |
554 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
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555 | } |
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556 | |||
557 | /** Write DTLB Synchronous Fault Status Register. |
||
558 | * |
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559 | * @param v New value of D-SFSR register. |
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560 | */ |
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1780 | jermar | 561 | static inline void dtlb_sfsr_write(uint64_t v) |
873 | jermar | 562 | { |
563 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
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1822 | jermar | 564 | membar(); |
873 | jermar | 565 | } |
566 | |||
567 | /** Read DTLB Synchronous Fault Address Register. |
||
568 | * |
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569 | * @return Current content of D-SFAR register. |
||
570 | */ |
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1780 | jermar | 571 | static inline uint64_t dtlb_sfar_read(void) |
873 | jermar | 572 | { |
573 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
||
574 | } |
||
575 | |||
617 | jermar | 576 | /** Perform IMMU TLB Demap Operation. |
577 | * |
||
3450 | rimsky | 578 | * @param type |
579 | * Selects between context and page demap |
||
580 | * (and entire MMU demap on US-III). |
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2054 | jermar | 581 | * @param context_encoding Specifies which Context register has Context ID for |
582 | * demap. |
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617 | jermar | 583 | * @param page Address which is on the page to be demapped. |
584 | */ |
||
1780 | jermar | 585 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 586 | { |
587 | tlb_demap_addr_t da; |
||
588 | page_address_t pg; |
||
589 | |||
590 | da.value = 0; |
||
591 | pg.address = page; |
||
592 | |||
593 | da.type = type; |
||
594 | da.context = context_encoding; |
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595 | da.vpn = pg.vpn; |
||
596 | |||
2054 | jermar | 597 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
598 | * address within the |
||
599 | * ASI */ |
||
3145 | jermar | 600 | flush_pipeline(); |
617 | jermar | 601 | } |
602 | |||
603 | /** Perform DMMU TLB Demap Operation. |
||
604 | * |
||
3450 | rimsky | 605 | * @param type |
606 | * Selects between context and page demap |
||
607 | * (and entire MMU demap on US-III). |
||
2054 | jermar | 608 | * @param context_encoding Specifies which Context register has Context ID for |
609 | * demap. |
||
617 | jermar | 610 | * @param page Address which is on the page to be demapped. |
611 | */ |
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1780 | jermar | 612 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 613 | { |
614 | tlb_demap_addr_t da; |
||
615 | page_address_t pg; |
||
616 | |||
617 | da.value = 0; |
||
618 | pg.address = page; |
||
619 | |||
620 | da.type = type; |
||
621 | da.context = context_encoding; |
||
622 | da.vpn = pg.vpn; |
||
623 | |||
2054 | jermar | 624 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
625 | * address within the |
||
626 | * ASI */ |
||
1822 | jermar | 627 | membar(); |
617 | jermar | 628 | } |
629 | |||
2231 | jermar | 630 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
631 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
||
632 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
||
863 | jermar | 633 | |
1780 | jermar | 634 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
897 | jermar | 635 | |
1946 | jermar | 636 | extern void dump_sfsr_and_sfar(void); |
637 | |||
1823 | jermar | 638 | #endif /* !def __ASM__ */ |
639 | |||
418 | jermar | 640 | #endif |
1702 | cejka | 641 | |
1822 | jermar | 642 | /** @} |
3493 | rimsky | 643 | */ |