Subversion Repositories HelenOS

Rev

Rev 3862 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
3743 rimsky 1
/*
2
 * Copyright (c) 2005 Jakub Jermar
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
29
/** @addtogroup sparc64mm  
30
 * @{
31
 */
32
/** @file
33
 */
34
 
35
#ifndef KERN_sparc64_sun4u_TLB_H_
36
#define KERN_sparc64_sun4u_TLB_H_
37
 
38
#if defined (US)
39
#define ITLB_ENTRY_COUNT        64
40
#define DTLB_ENTRY_COUNT        64
41
#define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
42
#endif
43
 
44
/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
45
#if defined (US3)
46
#define DTLB_MAX_LOCKED_ENTRIES     16
47
#endif
48
 
3770 rimsky 49
#define MEM_CONTEXT_KERNEL      0
50
#define MEM_CONTEXT_TEMP        1
51
 
3743 rimsky 52
/** Bit width of the TLB-locked portion of kernel address space. */
53
#define KERNEL_PAGE_WIDTH       22  /* 4M */
54
 
55
/* TLB Demap Operation types. */
56
#define TLB_DEMAP_PAGE      0
57
#define TLB_DEMAP_CONTEXT   1
58
#if defined (US3)
59
#define TLB_DEMAP_ALL       2
60
#endif
61
 
62
#define TLB_DEMAP_TYPE_SHIFT    6
63
 
64
/* TLB Demap Operation Context register encodings. */
65
#define TLB_DEMAP_PRIMARY   0
66
#define TLB_DEMAP_SECONDARY 1
67
#define TLB_DEMAP_NUCLEUS   2
68
 
69
/* There are more TLBs in one MMU in US3, their codes are defined here. */
70
#if defined (US3)
71
/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
72
#define TLB_DSMALL  0
73
#define TLB_DBIG_0  2
74
#define TLB_DBIG_1  3
75
 
76
/* I-MMU: one small (16-entry) TLB and one big TLB */
77
#define TLB_ISMALL  0
78
#define TLB_IBIG    2
79
#endif
80
 
81
#define TLB_DEMAP_CONTEXT_SHIFT 4
82
 
83
/* TLB Tag Access shifts */
84
#define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
85
#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
86
#define TLB_TAG_ACCESS_VPN_SHIFT    13
87
 
88
#ifndef __ASM__
89
 
3862 rimsky 90
#include <arch/mm/tte.h>
91
#include <arch/mm/mmu.h>
3743 rimsky 92
#include <arch/mm/page.h>
93
#include <arch/asm.h>
94
#include <arch/barrier.h>
95
#include <arch/types.h>
96
#include <arch/register.h>
3862 rimsky 97
#include <arch/cpu.h>
3743 rimsky 98
 
99
union tlb_context_reg {
100
    uint64_t v;
101
    struct {
102
        unsigned long : 51;
103
        unsigned context : 13;      /**< Context/ASID. */
104
    } __attribute__ ((packed));
105
};
106
typedef union tlb_context_reg tlb_context_reg_t;
107
 
108
/** I-/D-TLB Data In/Access Register type. */
109
typedef tte_data_t tlb_data_t;
110
 
111
/** I-/D-TLB Data Access Address in Alternate Space. */
112
 
113
#if defined (US)
114
 
115
union tlb_data_access_addr {
116
    uint64_t value;
117
    struct {
118
        uint64_t : 55;
119
        unsigned tlb_entry : 6;
120
        unsigned : 3;
121
    } __attribute__ ((packed));
122
};
123
typedef union tlb_data_access_addr dtlb_data_access_addr_t;
124
typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
125
typedef union tlb_data_access_addr itlb_data_access_addr_t;
126
typedef union tlb_data_access_addr itlb_tag_read_addr_t;
127
 
128
#elif defined (US3)
129
 
130
/*
131
 * In US3, I-MMU and D-MMU have different formats of the data
132
 * access register virtual address. In the corresponding
133
 * structures the member variable for the entry number is
3770 rimsky 134
 * called "local_tlb_entry" - it contrasts with the "tlb_entry"
3743 rimsky 135
 * for the US data access register VA structure. The rationale
136
 * behind this is to prevent careless mistakes in the code
137
 * caused by setting only the entry number and not the TLB
138
 * number in the US3 code (when taking the code from US).
139
 */
140
 
141
union dtlb_data_access_addr {
142
    uint64_t value;
143
    struct {
144
        uint64_t : 45;
145
        unsigned : 1;
146
        unsigned tlb_number : 2;
147
        unsigned : 4;
148
        unsigned local_tlb_entry : 9;
149
        unsigned : 3;
150
    } __attribute__ ((packed));
151
};
152
typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
153
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
154
 
155
union itlb_data_access_addr {
156
    uint64_t value;
157
    struct {
158
        uint64_t : 45;
159
        unsigned : 1;
160
        unsigned tlb_number : 2;
161
        unsigned : 6;
162
        unsigned local_tlb_entry : 7;
163
        unsigned : 3;
164
    } __attribute__ ((packed));
165
};
166
typedef union itlb_data_access_addr itlb_data_access_addr_t;
167
typedef union itlb_data_access_addr itlb_tag_read_addr_t;
168
 
169
#endif
170
 
171
/** I-/D-TLB Tag Read Register. */
172
union tlb_tag_read_reg {
173
    uint64_t value;
174
    struct {
175
        uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
176
        unsigned context : 13;  /**< Context identifier. */
177
    } __attribute__ ((packed));
178
};
179
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
180
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
181
 
182
 
183
/** TLB Demap Operation Address. */
184
union tlb_demap_addr {
185
    uint64_t value;
186
    struct {
187
        uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
188
#if defined (US)
189
        unsigned : 6;       /**< Ignored. */
190
        unsigned type : 1;  /**< The type of demap operation. */
191
#elif defined (US3)
192
        unsigned : 5;       /**< Ignored. */
193
        unsigned type: 2;   /**< The type of demap operation. */
194
#endif
195
        unsigned context : 2;   /**< Context register selection. */
196
        unsigned : 4;       /**< Zero. */
197
    } __attribute__ ((packed));
198
};
199
typedef union tlb_demap_addr tlb_demap_addr_t;
200
 
201
/** TLB Synchronous Fault Status Register. */
202
union tlb_sfsr_reg {
203
    uint64_t value;
204
    struct {
205
#if defined (US)
206
        unsigned long : 40; /**< Implementation dependent. */
207
        unsigned asi : 8;   /**< ASI. */
208
        unsigned : 2;
209
        unsigned ft : 7;    /**< Fault type. */
210
#elif defined (US3)
211
        unsigned long : 39; /**< Implementation dependent. */
212
        unsigned nf : 1;    /**< Non-faulting load. */
213
        unsigned asi : 8;   /**< ASI. */
214
        unsigned tm : 1;    /**< I-TLB miss. */
215
        unsigned : 3;       /**< Reserved. */
216
        unsigned ft : 5;    /**< Fault type. */
217
#endif
218
        unsigned e : 1;     /**< Side-effect bit. */
219
        unsigned ct : 2;    /**< Context Register selection. */
220
        unsigned pr : 1;    /**< Privilege bit. */
221
        unsigned w : 1;     /**< Write bit. */
222
        unsigned ow : 1;    /**< Overwrite bit. */
223
        unsigned fv : 1;    /**< Fault Valid bit. */
224
    } __attribute__ ((packed));
225
};
226
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
227
 
228
#if defined (US3)
229
 
230
/*
231
 * Functions for determining the number of entries in TLBs. They either return
232
 * a constant value or a value based on the CPU autodetection.
233
 */
234
 
235
/**
3770 rimsky 236
 * Determine the number of entries in the DMMU's small TLB.
3743 rimsky 237
 */
238
static inline uint16_t tlb_dsmall_size(void)
239
{
240
    return 16;
241
}
242
 
243
/**
3770 rimsky 244
 * Determine the number of entries in each DMMU's big TLB.
3743 rimsky 245
 */
246
static inline uint16_t tlb_dbig_size(void)
247
{
248
    return 512;
249
}
250
 
251
/**
3770 rimsky 252
 * Determine the number of entries in the IMMU's small TLB.
3743 rimsky 253
 */
254
static inline uint16_t tlb_ismall_size(void)
255
{
256
    return 16;
257
}
258
 
259
/**
3770 rimsky 260
 * Determine the number of entries in the IMMU's big TLB.
3743 rimsky 261
 */
262
static inline uint16_t tlb_ibig_size(void)
263
{
264
    if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
265
        return 512;
266
    else
267
        return 128;
268
}
269
 
270
#endif
271
 
272
/** Read MMU Primary Context Register.
273
 *
3770 rimsky 274
 * @return      Current value of Primary Context Register.
3743 rimsky 275
 */
276
static inline uint64_t mmu_primary_context_read(void)
277
{
278
    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
279
}
280
 
281
/** Write MMU Primary Context Register.
282
 *
3770 rimsky 283
 * @param v     New value of Primary Context Register.
3743 rimsky 284
 */
285
static inline void mmu_primary_context_write(uint64_t v)
286
{
287
    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
288
    flush_pipeline();
289
}
290
 
291
/** Read MMU Secondary Context Register.
292
 *
3770 rimsky 293
 * @return      Current value of Secondary Context Register.
3743 rimsky 294
 */
295
static inline uint64_t mmu_secondary_context_read(void)
296
{
297
    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
298
}
299
 
300
/** Write MMU Primary Context Register.
301
 *
3770 rimsky 302
 * @param v     New value of Primary Context Register.
3743 rimsky 303
 */
304
static inline void mmu_secondary_context_write(uint64_t v)
305
{
306
    asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
307
    flush_pipeline();
308
}
309
 
310
#if defined (US)
311
 
312
/** Read IMMU TLB Data Access Register.
313
 *
3770 rimsky 314
 * @param entry     TLB Entry index.
3743 rimsky 315
 *
3770 rimsky 316
 * @return      Current value of specified IMMU TLB Data Access
317
 *          Register.
3743 rimsky 318
 */
319
static inline uint64_t itlb_data_access_read(index_t entry)
320
{
321
    itlb_data_access_addr_t reg;
322
 
323
    reg.value = 0;
324
    reg.tlb_entry = entry;
325
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
326
}
327
 
328
/** Write IMMU TLB Data Access Register.
329
 *
3770 rimsky 330
 * @param entry     TLB Entry index.
331
 * @param value     Value to be written.
3743 rimsky 332
 */
333
static inline void itlb_data_access_write(index_t entry, uint64_t value)
334
{
335
    itlb_data_access_addr_t reg;
336
 
337
    reg.value = 0;
338
    reg.tlb_entry = entry;
339
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
340
    flush_pipeline();
341
}
342
 
343
/** Read DMMU TLB Data Access Register.
344
 *
3770 rimsky 345
 * @param entry     TLB Entry index.
3743 rimsky 346
 *
3770 rimsky 347
 * @return      Current value of specified DMMU TLB Data Access
348
 *          Register.
3743 rimsky 349
 */
350
static inline uint64_t dtlb_data_access_read(index_t entry)
351
{
352
    dtlb_data_access_addr_t reg;
353
 
354
    reg.value = 0;
355
    reg.tlb_entry = entry;
356
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
357
}
358
 
359
/** Write DMMU TLB Data Access Register.
360
 *
3770 rimsky 361
 * @param entry     TLB Entry index.
362
 * @param value     Value to be written.
3743 rimsky 363
 */
364
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
365
{
366
    dtlb_data_access_addr_t reg;
367
 
368
    reg.value = 0;
369
    reg.tlb_entry = entry;
370
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
371
    membar();
372
}
373
 
374
/** Read IMMU TLB Tag Read Register.
375
 *
3770 rimsky 376
 * @param entry     TLB Entry index.
3743 rimsky 377
 *
3770 rimsky 378
 * @return      Current value of specified IMMU TLB Tag Read Register.
3743 rimsky 379
 */
380
static inline uint64_t itlb_tag_read_read(index_t entry)
381
{
382
    itlb_tag_read_addr_t tag;
383
 
384
    tag.value = 0;
385
    tag.tlb_entry = entry;
386
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
387
}
388
 
389
/** Read DMMU TLB Tag Read Register.
390
 *
3770 rimsky 391
 * @param entry     TLB Entry index.
3743 rimsky 392
 *
3770 rimsky 393
 * @return      Current value of specified DMMU TLB Tag Read Register.
3743 rimsky 394
 */
395
static inline uint64_t dtlb_tag_read_read(index_t entry)
396
{
397
    dtlb_tag_read_addr_t tag;
398
 
399
    tag.value = 0;
400
    tag.tlb_entry = entry;
401
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
402
}
403
 
404
#elif defined (US3)
405
 
406
 
407
/** Read IMMU TLB Data Access Register.
408
 *
3770 rimsky 409
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
410
 * @param entry     TLB Entry index.
3743 rimsky 411
 *
3770 rimsky 412
 * @return      Current value of specified IMMU TLB Data Access
413
 *          Register.
3743 rimsky 414
 */
415
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
416
{
417
    itlb_data_access_addr_t reg;
418
 
419
    reg.value = 0;
420
    reg.tlb_number = tlb;
421
    reg.local_tlb_entry = entry;
422
    return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
423
}
424
 
425
/** Write IMMU TLB Data Access Register.
3770 rimsky 426
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
427
 * @param entry     TLB Entry index.
428
 * @param value     Value to be written.
3743 rimsky 429
 */
430
static inline void itlb_data_access_write(int tlb, index_t entry,
431
    uint64_t value)
432
{
433
    itlb_data_access_addr_t reg;
434
 
435
    reg.value = 0;
436
    reg.tlb_number = tlb;
437
    reg.local_tlb_entry = entry;
438
    asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
439
    flush_pipeline();
440
}
441
 
442
/** Read DMMU TLB Data Access Register.
443
 *
3770 rimsky 444
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
445
 * @param entry     TLB Entry index.
3743 rimsky 446
 *
3770 rimsky 447
 * @return      Current value of specified DMMU TLB Data Access
448
 *          Register.
3743 rimsky 449
 */
450
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
451
{
452
    dtlb_data_access_addr_t reg;
453
 
454
    reg.value = 0;
455
    reg.tlb_number = tlb;
456
    reg.local_tlb_entry = entry;
457
    return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
458
}
459
 
460
/** Write DMMU TLB Data Access Register.
461
 *
3770 rimsky 462
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
463
 * @param entry     TLB Entry index.
464
 * @param value     Value to be written.
3743 rimsky 465
 */
466
static inline void dtlb_data_access_write(int tlb, index_t entry,
467
    uint64_t value)
468
{
469
    dtlb_data_access_addr_t reg;
470
 
471
    reg.value = 0;
472
    reg.tlb_number = tlb;
473
    reg.local_tlb_entry = entry;
474
    asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
475
    membar();
476
}
477
 
478
/** Read IMMU TLB Tag Read Register.
479
 *
3770 rimsky 480
 * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
481
 * @param entry     TLB Entry index.
3743 rimsky 482
 *
3770 rimsky 483
 * @return      Current value of specified IMMU TLB Tag Read Register.
3743 rimsky 484
 */
485
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
486
{
487
    itlb_tag_read_addr_t tag;
488
 
489
    tag.value = 0;
490
    tag.tlb_number = tlb;
491
    tag.local_tlb_entry = entry;
492
    return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
493
}
494
 
495
/** Read DMMU TLB Tag Read Register.
496
 *
3770 rimsky 497
 * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
498
 * @param entry     TLB Entry index.
3743 rimsky 499
 *
3770 rimsky 500
 * @return      Current value of specified DMMU TLB Tag Read Register.
3743 rimsky 501
 */
502
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
503
{
504
    dtlb_tag_read_addr_t tag;
505
 
506
    tag.value = 0;
507
    tag.tlb_number = tlb;
508
    tag.local_tlb_entry = entry;
509
    return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
510
}
511
 
512
#endif
513
 
514
 
515
/** Write IMMU TLB Tag Access Register.
516
 *
3770 rimsky 517
 * @param v     Value to be written.
3743 rimsky 518
 */
519
static inline void itlb_tag_access_write(uint64_t v)
520
{
521
    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
522
    flush_pipeline();
523
}
524
 
525
/** Read IMMU TLB Tag Access Register.
526
 *
3770 rimsky 527
 * @return      Current value of IMMU TLB Tag Access Register.
3743 rimsky 528
 */
529
static inline uint64_t itlb_tag_access_read(void)
530
{
531
    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
532
}
533
 
534
/** Write DMMU TLB Tag Access Register.
535
 *
3770 rimsky 536
 * @param v     Value to be written.
3743 rimsky 537
 */
538
static inline void dtlb_tag_access_write(uint64_t v)
539
{
540
    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
541
    membar();
542
}
543
 
544
/** Read DMMU TLB Tag Access Register.
545
 *
3770 rimsky 546
 * @return      Current value of DMMU TLB Tag Access Register.
3743 rimsky 547
 */
548
static inline uint64_t dtlb_tag_access_read(void)
549
{
550
    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
551
}
552
 
553
 
554
/** Write IMMU TLB Data in Register.
555
 *
3770 rimsky 556
 * @param v     Value to be written.
3743 rimsky 557
 */
558
static inline void itlb_data_in_write(uint64_t v)
559
{
560
    asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
561
    flush_pipeline();
562
}
563
 
564
/** Write DMMU TLB Data in Register.
565
 *
3770 rimsky 566
 * @param v     Value to be written.
3743 rimsky 567
 */
568
static inline void dtlb_data_in_write(uint64_t v)
569
{
570
    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
571
    membar();
572
}
573
 
574
/** Read ITLB Synchronous Fault Status Register.
575
 *
3770 rimsky 576
 * @return      Current content of I-SFSR register.
3743 rimsky 577
 */
578
static inline uint64_t itlb_sfsr_read(void)
579
{
580
    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
581
}
582
 
583
/** Write ITLB Synchronous Fault Status Register.
584
 *
3770 rimsky 585
 * @param v     New value of I-SFSR register.
3743 rimsky 586
 */
587
static inline void itlb_sfsr_write(uint64_t v)
588
{
589
    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
590
    flush_pipeline();
591
}
592
 
593
/** Read DTLB Synchronous Fault Status Register.
594
 *
3770 rimsky 595
 * @return      Current content of D-SFSR register.
3743 rimsky 596
 */
597
static inline uint64_t dtlb_sfsr_read(void)
598
{
599
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
600
}
601
 
602
/** Write DTLB Synchronous Fault Status Register.
603
 *
3770 rimsky 604
 * @param v     New value of D-SFSR register.
3743 rimsky 605
 */
606
static inline void dtlb_sfsr_write(uint64_t v)
607
{
608
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
609
    membar();
610
}
611
 
612
/** Read DTLB Synchronous Fault Address Register.
613
 *
3770 rimsky 614
 * @return      Current content of D-SFAR register.
3743 rimsky 615
 */
616
static inline uint64_t dtlb_sfar_read(void)
617
{
618
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
619
}
620
 
621
/** Perform IMMU TLB Demap Operation.
622
 *
3770 rimsky 623
 * @param type      Selects between context and page demap (and entire MMU
624
 *          demap on US3).
3743 rimsky 625
 * @param context_encoding Specifies which Context register has Context ID for
3770 rimsky 626
 *          demap.
627
 * @param page      Address which is on the page to be demapped.
3743 rimsky 628
 */
629
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
630
{
631
    tlb_demap_addr_t da;
632
    page_address_t pg;
633
 
634
    da.value = 0;
635
    pg.address = page;
636
 
637
    da.type = type;
638
    da.context = context_encoding;
639
    da.vpn = pg.vpn;
640
 
3770 rimsky 641
    /* da.value is the address within the ASI */
642
    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
643
 
3743 rimsky 644
    flush_pipeline();
645
}
646
 
647
/** Perform DMMU TLB Demap Operation.
648
 *
3770 rimsky 649
 * @param type      Selects between context and page demap (and entire MMU
650
 *          demap on US3).
3743 rimsky 651
 * @param context_encoding Specifies which Context register has Context ID for
3770 rimsky 652
 *          demap.
653
 * @param page      Address which is on the page to be demapped.
3743 rimsky 654
 */
655
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
656
{
657
    tlb_demap_addr_t da;
658
    page_address_t pg;
659
 
660
    da.value = 0;
661
    pg.address = page;
662
 
663
    da.type = type;
664
    da.context = context_encoding;
665
    da.vpn = pg.vpn;
666
 
3770 rimsky 667
    /* da.value is the address within the ASI */
668
    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
669
 
3743 rimsky 670
    membar();
671
}
672
 
3770 rimsky 673
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
674
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
675
extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
3743 rimsky 676
 
3770 rimsky 677
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
3743 rimsky 678
 
4130 rimsky 679
extern void describe_dmmu_fault(void);
3743 rimsky 680
 
681
#endif /* !def __ASM__ */
682
 
683
#endif
684
 
685
/** @}
686
 */