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418 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1784 | jermar | 29 | /** @addtogroup sparc64 |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
1784 | jermar | 35 | #ifndef KERN_sparc64_ASM_H_ |
36 | #define KERN_sparc64_ASM_H_ |
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418 | jermar | 37 | |
2089 | decky | 38 | #include <arch/arch.h> |
418 | jermar | 39 | #include <arch/types.h> |
3071 | decky | 40 | #include <typedefs.h> |
2089 | decky | 41 | #include <align.h> |
650 | jermar | 42 | #include <arch/register.h> |
418 | jermar | 43 | #include <config.h> |
1885 | jermar | 44 | #include <arch/stack.h> |
418 | jermar | 45 | |
650 | jermar | 46 | /** Read Processor State register. |
47 | * |
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48 | * @return Value of PSTATE register. |
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49 | */ |
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1780 | jermar | 50 | static inline uint64_t pstate_read(void) |
650 | jermar | 51 | { |
1780 | jermar | 52 | uint64_t v; |
650 | jermar | 53 | |
2082 | decky | 54 | asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
650 | jermar | 55 | |
56 | return v; |
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57 | } |
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58 | |||
59 | /** Write Processor State register. |
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60 | * |
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1708 | jermar | 61 | * @param v New value of PSTATE register. |
650 | jermar | 62 | */ |
1780 | jermar | 63 | static inline void pstate_write(uint64_t v) |
650 | jermar | 64 | { |
2082 | decky | 65 | asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
650 | jermar | 66 | } |
67 | |||
658 | jermar | 68 | /** Read TICK_compare Register. |
69 | * |
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70 | * @return Value of TICK_comapre register. |
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71 | */ |
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1780 | jermar | 72 | static inline uint64_t tick_compare_read(void) |
658 | jermar | 73 | { |
1780 | jermar | 74 | uint64_t v; |
658 | jermar | 75 | |
2082 | decky | 76 | asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
658 | jermar | 77 | |
78 | return v; |
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79 | } |
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650 | jermar | 80 | |
658 | jermar | 81 | /** Write TICK_compare Register. |
82 | * |
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1708 | jermar | 83 | * @param v New value of TICK_comapre register. |
658 | jermar | 84 | */ |
1780 | jermar | 85 | static inline void tick_compare_write(uint64_t v) |
658 | jermar | 86 | { |
2082 | decky | 87 | asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
658 | jermar | 88 | } |
89 | |||
90 | /** Read TICK Register. |
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91 | * |
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92 | * @return Value of TICK register. |
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93 | */ |
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1780 | jermar | 94 | static inline uint64_t tick_read(void) |
658 | jermar | 95 | { |
1780 | jermar | 96 | uint64_t v; |
658 | jermar | 97 | |
2082 | decky | 98 | asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
658 | jermar | 99 | |
100 | return v; |
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101 | } |
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102 | |||
103 | /** Write TICK Register. |
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104 | * |
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1708 | jermar | 105 | * @param v New value of TICK register. |
658 | jermar | 106 | */ |
1780 | jermar | 107 | static inline void tick_write(uint64_t v) |
658 | jermar | 108 | { |
2082 | decky | 109 | asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
658 | jermar | 110 | } |
111 | |||
1882 | jermar | 112 | /** Read FPRS Register. |
113 | * |
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114 | * @return Value of FPRS register. |
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115 | */ |
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116 | static inline uint64_t fprs_read(void) |
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117 | { |
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118 | uint64_t v; |
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119 | |||
2082 | decky | 120 | asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
1882 | jermar | 121 | |
122 | return v; |
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123 | } |
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124 | |||
125 | /** Write FPRS Register. |
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126 | * |
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127 | * @param v New value of FPRS register. |
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128 | */ |
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129 | static inline void fprs_write(uint64_t v) |
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130 | { |
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2082 | decky | 131 | asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
1882 | jermar | 132 | } |
133 | |||
664 | jermar | 134 | /** Read SOFTINT Register. |
135 | * |
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136 | * @return Value of SOFTINT register. |
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137 | */ |
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1780 | jermar | 138 | static inline uint64_t softint_read(void) |
664 | jermar | 139 | { |
1780 | jermar | 140 | uint64_t v; |
658 | jermar | 141 | |
2082 | decky | 142 | asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
664 | jermar | 143 | |
144 | return v; |
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145 | } |
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146 | |||
147 | /** Write SOFTINT Register. |
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148 | * |
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1708 | jermar | 149 | * @param v New value of SOFTINT register. |
664 | jermar | 150 | */ |
1780 | jermar | 151 | static inline void softint_write(uint64_t v) |
664 | jermar | 152 | { |
2082 | decky | 153 | asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
664 | jermar | 154 | } |
155 | |||
665 | jermar | 156 | /** Write CLEAR_SOFTINT Register. |
157 | * |
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158 | * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
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159 | * |
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1708 | jermar | 160 | * @param v New value of CLEAR_SOFTINT register. |
665 | jermar | 161 | */ |
1780 | jermar | 162 | static inline void clear_softint_write(uint64_t v) |
665 | jermar | 163 | { |
2082 | decky | 164 | asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
665 | jermar | 165 | } |
166 | |||
1849 | jermar | 167 | /** Write SET_SOFTINT Register. |
168 | * |
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169 | * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
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170 | * |
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171 | * @param v New value of SET_SOFTINT register. |
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172 | */ |
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173 | static inline void set_softint_write(uint64_t v) |
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174 | { |
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2082 | decky | 175 | asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
1849 | jermar | 176 | } |
177 | |||
418 | jermar | 178 | /** Enable interrupts. |
179 | * |
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180 | * Enable interrupts and return previous |
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181 | * value of IPL. |
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182 | * |
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183 | * @return Old interrupt priority level. |
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184 | */ |
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185 | static inline ipl_t interrupts_enable(void) { |
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650 | jermar | 186 | pstate_reg_t pstate; |
1780 | jermar | 187 | uint64_t value; |
650 | jermar | 188 | |
189 | value = pstate_read(); |
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190 | pstate.value = value; |
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191 | pstate.ie = true; |
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192 | pstate_write(pstate.value); |
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193 | |||
194 | return (ipl_t) value; |
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418 | jermar | 195 | } |
196 | |||
197 | /** Disable interrupts. |
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198 | * |
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199 | * Disable interrupts and return previous |
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200 | * value of IPL. |
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201 | * |
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202 | * @return Old interrupt priority level. |
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203 | */ |
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204 | static inline ipl_t interrupts_disable(void) { |
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650 | jermar | 205 | pstate_reg_t pstate; |
1780 | jermar | 206 | uint64_t value; |
650 | jermar | 207 | |
208 | value = pstate_read(); |
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209 | pstate.value = value; |
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210 | pstate.ie = false; |
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211 | pstate_write(pstate.value); |
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212 | |||
213 | return (ipl_t) value; |
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418 | jermar | 214 | } |
215 | |||
216 | /** Restore interrupt priority level. |
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217 | * |
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218 | * Restore IPL. |
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219 | * |
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220 | * @param ipl Saved interrupt priority level. |
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221 | */ |
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222 | static inline void interrupts_restore(ipl_t ipl) { |
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650 | jermar | 223 | pstate_reg_t pstate; |
224 | |||
225 | pstate.value = pstate_read(); |
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226 | pstate.ie = ((pstate_reg_t) ipl).ie; |
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227 | pstate_write(pstate.value); |
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418 | jermar | 228 | } |
229 | |||
230 | /** Return interrupt priority level. |
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231 | * |
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232 | * Return IPL. |
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233 | * |
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234 | * @return Current interrupt priority level. |
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235 | */ |
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236 | static inline ipl_t interrupts_read(void) { |
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650 | jermar | 237 | return (ipl_t) pstate_read(); |
418 | jermar | 238 | } |
239 | |||
240 | /** Return base address of current stack. |
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241 | * |
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242 | * Return the base address of the current stack. |
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243 | * The stack is assumed to be STACK_SIZE bytes long. |
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244 | * The stack must start on page boundary. |
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245 | */ |
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1780 | jermar | 246 | static inline uintptr_t get_stack_base(void) |
418 | jermar | 247 | { |
1885 | jermar | 248 | uintptr_t unbiased_sp; |
426 | jermar | 249 | |
2082 | decky | 250 | asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
426 | jermar | 251 | |
1885 | jermar | 252 | return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
418 | jermar | 253 | } |
254 | |||
640 | jermar | 255 | /** Read Version Register. |
256 | * |
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257 | * @return Value of VER register. |
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258 | */ |
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1780 | jermar | 259 | static inline uint64_t ver_read(void) |
640 | jermar | 260 | { |
1780 | jermar | 261 | uint64_t v; |
640 | jermar | 262 | |
2082 | decky | 263 | asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
640 | jermar | 264 | |
265 | return v; |
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266 | } |
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267 | |||
2068 | jermar | 268 | /** Read Trap Program Counter register. |
529 | jermar | 269 | * |
2068 | jermar | 270 | * @return Current value in TPC. |
529 | jermar | 271 | */ |
2068 | jermar | 272 | static inline uint64_t tpc_read(void) |
529 | jermar | 273 | { |
1780 | jermar | 274 | uint64_t v; |
529 | jermar | 275 | |
2082 | decky | 276 | asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
529 | jermar | 277 | |
278 | return v; |
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279 | } |
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280 | |||
2068 | jermar | 281 | /** Read Trap Level register. |
873 | jermar | 282 | * |
2068 | jermar | 283 | * @return Current value in TL. |
873 | jermar | 284 | */ |
2068 | jermar | 285 | static inline uint64_t tl_read(void) |
873 | jermar | 286 | { |
1780 | jermar | 287 | uint64_t v; |
873 | jermar | 288 | |
2082 | decky | 289 | asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
873 | jermar | 290 | |
291 | return v; |
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292 | } |
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293 | |||
2068 | jermar | 294 | /** Read Trap Base Address register. |
883 | jermar | 295 | * |
2068 | jermar | 296 | * @return Current value in TBA. |
883 | jermar | 297 | */ |
2068 | jermar | 298 | static inline uint64_t tba_read(void) |
883 | jermar | 299 | { |
1780 | jermar | 300 | uint64_t v; |
883 | jermar | 301 | |
2082 | decky | 302 | asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
883 | jermar | 303 | |
304 | return v; |
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305 | } |
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873 | jermar | 306 | |
529 | jermar | 307 | /** Write Trap Base Address register. |
308 | * |
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1708 | jermar | 309 | * @param v New value of TBA. |
529 | jermar | 310 | */ |
1780 | jermar | 311 | static inline void tba_write(uint64_t v) |
529 | jermar | 312 | { |
2082 | decky | 313 | asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
529 | jermar | 314 | } |
315 | |||
1780 | jermar | 316 | /** Load uint64_t from alternate space. |
569 | jermar | 317 | * |
318 | * @param asi ASI determining the alternate space. |
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319 | * @param va Virtual address within the ASI. |
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320 | * |
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321 | * @return Value read from the virtual address in the specified address space. |
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322 | */ |
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1780 | jermar | 323 | static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
569 | jermar | 324 | { |
1780 | jermar | 325 | uint64_t v; |
569 | jermar | 326 | |
2082 | decky | 327 | asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
569 | jermar | 328 | |
329 | return v; |
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330 | } |
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529 | jermar | 331 | |
1780 | jermar | 332 | /** Store uint64_t to alternate space. |
569 | jermar | 333 | * |
334 | * @param asi ASI determining the alternate space. |
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335 | * @param va Virtual address within the ASI. |
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336 | * @param v Value to be written. |
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337 | */ |
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1780 | jermar | 338 | static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
569 | jermar | 339 | { |
2082 | decky | 340 | asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
569 | jermar | 341 | } |
342 | |||
1855 | jermar | 343 | /** Flush all valid register windows to memory. */ |
344 | static inline void flushw(void) |
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345 | { |
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2082 | decky | 346 | asm volatile ("flushw\n"); |
1855 | jermar | 347 | } |
348 | |||
1865 | jermar | 349 | /** Switch to nucleus by setting TL to 1. */ |
350 | static inline void nucleus_enter(void) |
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351 | { |
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2082 | decky | 352 | asm volatile ("wrpr %g0, 1, %tl\n"); |
1865 | jermar | 353 | } |
354 | |||
355 | /** Switch from nucleus by setting TL to 0. */ |
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356 | static inline void nucleus_leave(void) |
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357 | { |
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2082 | decky | 358 | asm volatile ("wrpr %g0, %g0, %tl\n"); |
1865 | jermar | 359 | } |
360 | |||
3477 | rimsky | 361 | /** Read UPA_CONFIG/FIREPLANE_CONFIG register. |
1899 | jermar | 362 | * |
3477 | rimsky | 363 | * @return |
364 | * Value of the UPA_CONFIG register in US, |
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365 | * value of the FIREPLANE_CONFIG on US3. |
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1899 | jermar | 366 | */ |
367 | static inline uint64_t upa_config_read(void) |
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368 | { |
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369 | return asi_u64_read(ASI_UPA_CONFIG, 0); |
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370 | } |
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371 | |||
1856 | jermar | 372 | extern void cpu_halt(void); |
373 | extern void cpu_sleep(void); |
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1881 | jermar | 374 | extern void asm_delay_loop(const uint32_t usec); |
418 | jermar | 375 | |
1856 | jermar | 376 | extern uint64_t read_from_ag_g7(void); |
377 | extern void write_to_ag_g6(uint64_t val); |
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378 | extern void write_to_ag_g7(uint64_t val); |
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379 | extern void write_to_ig_g6(uint64_t val); |
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380 | |||
1864 | jermar | 381 | extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
1860 | jermar | 382 | |
418 | jermar | 383 | #endif |
1702 | cejka | 384 | |
1784 | jermar | 385 | /** @} |
1702 | cejka | 386 | */ |