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1810 decky 1
/*
2071 jermar 2
 * Copyright (c) 2006 Martin Decky
1810 decky 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1952 jermar 29
/** @addtogroup ia32xen
1810 decky 30
 * @{
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 */
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/** @file
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 */
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#include <arch/pm.h>
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#include <config.h>
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#include <arch/types.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <arch/context.h>
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#include <panic.h>
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#include <arch/mm/page.h>
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#include <mm/slab.h>
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#include <memstr.h>
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#include <interrupt.h>
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/*
1952 jermar 48
 * Early ia32xen configuration functions and data structures.
1810 decky 49
 */
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/*
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 * We have no use for segmentation so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 *
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 * One is for GS register which holds pointer to the TLS thread
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 * structure in it's base.
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 */
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descriptor_t gdt[GDT_ITEMS] = {
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    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* KDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* UTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* UDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* TSS descriptor - set up will be completed later */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* TLS descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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};
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1829 decky 76
static trap_info_t traps[IDT_ITEMS + 1];
1810 decky 77
 
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static tss_t tss;
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tss_t *tss_p = NULL;
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/* gdtr is changed by kmp before next CPU is initialized */
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ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
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ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
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void gdt_setbase(descriptor_t *d, uintptr_t base)
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{
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    d->base_0_15 = base & 0xffff;
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    d->base_16_23 = ((base) >> 16) & 0xff;
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    d->base_24_31 = ((base) >> 24) & 0xff;
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}
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void gdt_setlimit(descriptor_t *d, uint32_t limit)
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{
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    d->limit_0_15 = limit & 0xffff;
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    d->limit_16_19 = (limit >> 16) & 0xf;
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}
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void tss_initialize(tss_t *t)
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{
3104 svoboda 101
    memsetb(t, sizeof(struct tss), 0);
1810 decky 102
}
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1831 decky 104
static void trap(void)
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{
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}
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1829 decky 108
void traps_init(void)
1810 decky 109
{
1829 decky 110
    index_t i;
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1810 decky 112
    for (i = 0; i < IDT_ITEMS; i++) {
1829 decky 113
        traps[i].vector = i;
1810 decky 114
 
1829 decky 115
        if (i == VECTOR_SYSCALL)
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            traps[i].flags = 3;
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        else
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            traps[i].flags = 0;
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        traps[i].cs = XEN_CS;
1831 decky 121
        traps[i].address = trap;
1810 decky 122
    }
1829 decky 123
    traps[IDT_ITEMS].vector = 0;
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    traps[IDT_ITEMS].flags = 0;
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    traps[IDT_ITEMS].cs = 0;
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    traps[IDT_ITEMS].address = NULL;
1810 decky 127
}
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129
 
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/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
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static void clean_IOPL_NT_flags(void)
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{
2082 decky 133
//  asm volatile (
1816 decky 134
//      "pushfl\n"
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//      "pop %%eax\n"
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//      "and $0xffff8fff, %%eax\n"
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//      "push %%eax\n"
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//      "popfl\n"
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//      : : : "eax"
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//  );
1810 decky 141
}
142
 
143
/* Clean AM(18) flag in CR0 register */
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static void clean_AM_flag(void)
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{
2082 decky 146
//  asm volatile (
1816 decky 147
//      "mov %%cr0, %%eax\n"
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//      "and $0xfffbffff, %%eax\n"
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//      "mov %%eax, %%cr0\n"
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//      : : : "eax"
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//  );
1810 decky 152
}
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154
void pm_init(void)
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{
156
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
157
 
1816 decky 158
//  gdtr_load(&gdtr);
1810 decky 159
 
1829 decky 160
    if (config.cpu_active == 1) {
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        traps_init();
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        xen_set_trap_table(traps);
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        /*
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         * NOTE: bootstrap CPU has statically allocated TSS, because
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         * the heap hasn't been initialized so far.
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         */
1810 decky 167
        tss_p = &tss;
1829 decky 168
    } else {
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        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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        if (!tss_p)
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            panic("could not allocate TSS\n");
172
    }
1810 decky 173
 
1816 decky 174
//  tss_initialize(tss_p);
1810 decky 175
 
176
    gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
177
    gdt_p[TSS_DES].special = 1;
178
    gdt_p[TSS_DES].granularity = 0;
179
 
180
    gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
181
    gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
182
 
183
    /*
184
     * As of this moment, the current CPU has its own GDT pointing
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     * to its own TSS. We just need to load the TR register.
186
     */
1816 decky 187
//  tr_load(selector(TSS_DES));
1810 decky 188
 
189
    clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
190
    clean_AM_flag();          /* Disable alignment check */
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}
192
 
193
void set_tls_desc(uintptr_t tls)
194
{
195
    ptr_16_32_t cpugdtr;
196
    descriptor_t *gdt_p;
197
 
198
    gdtr_store(&cpugdtr);
199
    gdt_p = (descriptor_t *) cpugdtr.base;
200
    gdt_setbase(&gdt_p[TLS_DES], tls);
201
    /* Reload gdt register to update GS in CPU */
202
    gdtr_load(&cpugdtr);
203
}
204
 
205
/** @}
206
 */