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1018 decky 1
#
2071 jermar 2
# Copyright (c) 2006 Martin Decky
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# Copyright (c) 2006 Jakub Jermar 
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#include <stack.h>
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#include <register.h>
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.register       %g2, #scratch
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.register       %g3, #scratch
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.text
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.global halt
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.global memcpy
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.global jump_to_kernel
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halt:
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	b halt
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	nop
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memcpy:
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	mov	%o0, %o3		! save dst
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	add	%o1, 7, %g1
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	and	%g1, -8, %g1
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	cmp	%o1, %g1
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	be,pn	%xcc, 3f
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	add	%o0, 7, %g1
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	mov	0, %g3
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0:
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	brz,pn	%o2, 2f
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	mov	0, %g2
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1:
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	ldub	[%g3 + %o1], %g1
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	add	%g2, 1, %g2
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	cmp	%o2, %g2
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	stb	%g1, [%g3 + %o0]
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	bne,pt	%xcc, 1b
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	mov	%g2, %g3
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2:
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	jmp	%o7 + 8			! exit point
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	mov	%o3, %o0
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3:
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	and	%g1, -8, %g1
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	cmp	%o0, %g1
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	bne,pt	%xcc, 0b
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	mov	0, %g3
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	srlx	%o2, 3, %g4
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	brz,pn	%g4, 5f
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	mov	0, %g5
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4:
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	sllx	%g3, 3, %g2
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	add	%g5, 1, %g3
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	ldx	[%o1 + %g2], %g1
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	mov	%g3, %g5
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	cmp	%g4, %g3
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	bne,pt	%xcc, 4b
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	stx	%g1, [%o0 + %g2]
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5:
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	and	%o2, 7, %o2
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	brz,pn	%o2, 2b
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	sllx	%g4, 3, %g1
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	mov	0, %g2
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	add	%g1, %o0, %o0
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	add	%g1, %o1, %g4
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	mov	0, %g3
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6:
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	ldub	[%g2 + %g4], %g1
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	stb	%g1, [%g2 + %o0]
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	add	%g3, 1, %g2
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	cmp	%o2, %g2
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	bne,pt	%xcc, 6b
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	mov	%g2, %g3
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	jmp	%o7 + 8			! exit point
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	mov	%o3, %o0
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jump_to_kernel:
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	/*
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	 * We have copied code and now we need to guarantee cache coherence.
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	 * 1. Make sure that the code we have moved has drained to main memory.
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	 * 2. Invalidate I-cache.
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	 * 3. Flush instruction pipeline.
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	 */
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#if defined (SUN4U)
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	/*
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	 * US3 processors have a write-invalidate cache, so explicitly
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	 * invalidating it is not required. Whether to invalidate I-cache
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	 * or not is decided according to the value of the global
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	 * "subarchitecture" variable (set in the bootstrap).
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	 */
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	set subarchitecture, %g2
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	ldub [%g2], %g2
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	cmp %g2, 3
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	be 1f
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	nop
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0:
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	call icache_flush
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	nop
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#endif
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1:
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	membar #StoreStore
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	/*
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	 * Flush the instruction pipeline.
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	 */
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	flush	%i7
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	mov %o0, %l1
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	mov %o1, %o0
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	mov %o2, %o1
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	mov %o3, %o2
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	jmp %l1				! jump to kernel
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	nop
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#define ICACHE_SIZE		8192
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#define ICACHE_LINE_SIZE	32
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#define ICACHE_SET_BIT		(1 << 13)
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#define ASI_ICACHE_TAG		0x67
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# Flush I-cache
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icache_flush:
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	set	((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1
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	stxa	%g0, [%g1] ASI_ICACHE_TAG
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0:	membar	#Sync
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	subcc	%g1, ICACHE_LINE_SIZE, %g1
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	bnz,pt	%xcc, 0b
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	stxa	%g0, [%g1] ASI_ICACHE_TAG
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	membar	#Sync
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	retl
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	! SF Erratum #51
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	nop
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.global ofw
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ofw:
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	save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
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	set ofw_cif, %l0
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	ldx [%l0], %l0
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	rdpr  %pstate, %l1
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	and  %l1, ~PSTATE_AM_BIT, %l2
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	wrpr  %l2, 0, %pstate
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	jmpl %l0, %o7
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	mov %i0, %o0
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	wrpr %l1, 0, %pstate
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	ret
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	restore %o0, 0, %o0