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1 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2001-2004 Jakub Jermar
1 jermar 3
 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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4148 decky 29
/** @addtogroup ia32
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 * @{
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 */
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/**
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 * @file
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 * @brief i8254 chip driver.
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 *
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 * Low level time functions.
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 */
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#include <arch/types.h>
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#include <time/clock.h>
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#include <time/delay.h>
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#include <arch/cycle.h>
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#include <arch/interrupt.h>
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#include <arch/drivers/i8259.h>
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#include <arch/drivers/i8254.h>
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#include <cpu.h>
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#include <config.h>
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#include <arch/pm.h>
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#include <arch/asm.h>
195 vana 50
#include <arch/cpuid.h>
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#include <arch.h>
195 vana 52
#include <time/delay.h>
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#include <ddi/irq.h>
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#include <ddi/device.h>
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#define CLK_PORT1   ((ioport8_t *)0x40)
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#define CLK_PORT4   ((ioport8_t *)0x43)
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#define CLK_CONST   1193180
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#define MAGIC_NUMBER    1194
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static irq_t i8254_irq;
576 palkovsky 63
 
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static irq_ownership_t i8254_claim(irq_t *irq)
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{
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    return IRQ_ACCEPT;
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}
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3906 jermar 69
static void i8254_irq_handler(irq_t *irq)
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{
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    /*
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     * This IRQ is responsible for kernel preemption.
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     * Nevertheless, we are now holding a spinlock which prevents
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     * preemption. For this particular IRQ, we don't need the
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     * lock. We just release it, call clock() and then reacquire it again.
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     */
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    spinlock_unlock(&irq->lock);
1956 decky 78
    clock();
2107 jermar 79
    spinlock_lock(&irq->lock);
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}
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1 jermar 82
void i8254_init(void)
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{
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    irq_initialize(&i8254_irq);
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    i8254_irq.preack = true;
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    i8254_irq.devno = device_assign_devno();
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    i8254_irq.inr = IRQ_CLK;
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    i8254_irq.claim = i8254_claim;
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    i8254_irq.handler = i8254_irq_handler;
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    irq_register(&i8254_irq);
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1 jermar 92
    i8254_normal_operation();
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}
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void i8254_normal_operation(void)
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{
3902 jermar 97
    pio_write_8(CLK_PORT4, 0x36);
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    pic_disable_irqs(1 << IRQ_CLK);
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    pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
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    pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8);
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    pic_enable_irqs(1 << IRQ_CLK);
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}
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#define LOOPS 150000
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#define SHIFT 11
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void i8254_calibrate_delay_loop(void)
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{
1780 jermar 108
    uint64_t clk1, clk2;
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    uint32_t t1, t2, o1, o2;
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    uint8_t not_ok;
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    /*
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     * One-shot timer. Count-down from 0xffff at 1193180Hz
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     * MAGIC_NUMBER is the magic value for 1ms.
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     */
3902 jermar 117
    pio_write_8(CLK_PORT4, 0x30);
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    pio_write_8(CLK_PORT1, 0xff);
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    pio_write_8(CLK_PORT1, 0xff);
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    do {
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        /* will read both status and count */
3902 jermar 123
        pio_write_8(CLK_PORT4, 0xc2);
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        not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1);
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        t1 = pio_read_8(CLK_PORT1);
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        t1 |= pio_read_8(CLK_PORT1) << 8;
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    } while (not_ok);
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    asm_delay_loop(LOOPS);
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3902 jermar 131
    pio_write_8(CLK_PORT4, 0xd2);
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    t2 = pio_read_8(CLK_PORT1);
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    t2 |= pio_read_8(CLK_PORT1) << 8;
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    /*
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     * We want to determine the overhead of the calibrating mechanism.
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     */
3902 jermar 138
    pio_write_8(CLK_PORT4, 0xd2);
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    o1 = pio_read_8(CLK_PORT1);
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    o1 |= pio_read_8(CLK_PORT1) << 8;
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142
    asm_fake_loop(LOOPS);
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3902 jermar 144
    pio_write_8(CLK_PORT4, 0xd2);
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    o2 = pio_read_8(CLK_PORT1);
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    o2 |= pio_read_8(CLK_PORT1) << 8;
1 jermar 147
 
2107 jermar 148
    CPU->delay_loop_const =
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        ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) +
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        (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0);
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2018 decky 152
    clk1 = get_cycle();
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    delay(1 << SHIFT);
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    clk2 = get_cycle();
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2018 decky 156
    CPU->frequency_mhz = (clk2 - clk1) >> SHIFT;
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158
    return;
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}
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1754 jermar 161
/** @}
1702 cejka 162
 */