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1810 | decky | 1 | /* |
1840 | decky | 2 | * Copyright (C) 2006 Martin Decky |
1810 | decky | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1952 | jermar | 29 | /** @addtogroup ia32xen |
1810 | decky | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
35 | #include <arch/pm.h> |
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36 | #include <config.h> |
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37 | #include <arch/types.h> |
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38 | #include <typedefs.h> |
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39 | #include <arch/interrupt.h> |
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40 | #include <arch/asm.h> |
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41 | #include <arch/context.h> |
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42 | #include <panic.h> |
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43 | #include <arch/mm/page.h> |
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44 | #include <mm/slab.h> |
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45 | #include <memstr.h> |
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46 | #include <arch/boot/boot.h> |
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47 | #include <interrupt.h> |
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48 | |||
49 | /* |
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1952 | jermar | 50 | * Early ia32xen configuration functions and data structures. |
1810 | decky | 51 | */ |
52 | |||
53 | /* |
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54 | * We have no use for segmentation so we set up flat mode. In this |
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55 | * mode, we use, for each privilege level, two segments spanning the |
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56 | * whole memory. One is for code and one is for data. |
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57 | * |
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58 | * One is for GS register which holds pointer to the TLS thread |
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59 | * structure in it's base. |
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60 | */ |
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61 | descriptor_t gdt[GDT_ITEMS] = { |
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62 | /* NULL descriptor */ |
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63 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
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64 | /* KTEXT descriptor */ |
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65 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
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66 | /* KDATA descriptor */ |
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67 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 }, |
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68 | /* UTEXT descriptor */ |
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69 | { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
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70 | /* UDATA descriptor */ |
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71 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
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72 | /* TSS descriptor - set up will be completed later */ |
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73 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
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74 | /* TLS descriptor */ |
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75 | { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, |
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76 | }; |
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77 | |||
1829 | decky | 78 | static trap_info_t traps[IDT_ITEMS + 1]; |
1810 | decky | 79 | |
80 | static tss_t tss; |
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81 | |||
82 | tss_t *tss_p = NULL; |
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83 | |||
84 | /* gdtr is changed by kmp before next CPU is initialized */ |
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85 | ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) }; |
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86 | ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt }; |
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87 | |||
88 | void gdt_setbase(descriptor_t *d, uintptr_t base) |
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89 | { |
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90 | d->base_0_15 = base & 0xffff; |
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91 | d->base_16_23 = ((base) >> 16) & 0xff; |
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92 | d->base_24_31 = ((base) >> 24) & 0xff; |
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93 | } |
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94 | |||
95 | void gdt_setlimit(descriptor_t *d, uint32_t limit) |
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96 | { |
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97 | d->limit_0_15 = limit & 0xffff; |
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98 | d->limit_16_19 = (limit >> 16) & 0xf; |
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99 | } |
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100 | |||
101 | void tss_initialize(tss_t *t) |
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102 | { |
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103 | memsetb((uintptr_t) t, sizeof(struct tss), 0); |
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104 | } |
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105 | |||
1831 | decky | 106 | static void trap(void) |
107 | { |
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108 | } |
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109 | |||
1829 | decky | 110 | void traps_init(void) |
1810 | decky | 111 | { |
1829 | decky | 112 | index_t i; |
113 | |||
1810 | decky | 114 | for (i = 0; i < IDT_ITEMS; i++) { |
1829 | decky | 115 | traps[i].vector = i; |
1810 | decky | 116 | |
1829 | decky | 117 | if (i == VECTOR_SYSCALL) |
118 | traps[i].flags = 3; |
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119 | else |
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120 | traps[i].flags = 0; |
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121 | |||
122 | traps[i].cs = XEN_CS; |
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1831 | decky | 123 | traps[i].address = trap; |
1810 | decky | 124 | exc_register(i, "undef", (iroutine) null_interrupt); |
125 | } |
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1829 | decky | 126 | traps[IDT_ITEMS].vector = 0; |
127 | traps[IDT_ITEMS].flags = 0; |
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128 | traps[IDT_ITEMS].cs = 0; |
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129 | traps[IDT_ITEMS].address = NULL; |
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130 | |||
1810 | decky | 131 | exc_register(13, "gp_fault", (iroutine) gp_fault); |
132 | exc_register( 7, "nm_fault", (iroutine) nm_fault); |
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133 | exc_register(12, "ss_fault", (iroutine) ss_fault); |
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134 | exc_register(19, "simd_fp", (iroutine) simd_fp_exception); |
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135 | } |
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136 | |||
137 | |||
138 | /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */ |
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139 | static void clean_IOPL_NT_flags(void) |
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140 | { |
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1816 | decky | 141 | // __asm__ volatile ( |
142 | // "pushfl\n" |
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143 | // "pop %%eax\n" |
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144 | // "and $0xffff8fff, %%eax\n" |
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145 | // "push %%eax\n" |
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146 | // "popfl\n" |
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147 | // : : : "eax" |
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148 | // ); |
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1810 | decky | 149 | } |
150 | |||
151 | /* Clean AM(18) flag in CR0 register */ |
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152 | static void clean_AM_flag(void) |
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153 | { |
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1816 | decky | 154 | // __asm__ volatile ( |
155 | // "mov %%cr0, %%eax\n" |
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156 | // "and $0xfffbffff, %%eax\n" |
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157 | // "mov %%eax, %%cr0\n" |
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158 | // : : : "eax" |
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159 | // ); |
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1810 | decky | 160 | } |
161 | |||
162 | void pm_init(void) |
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163 | { |
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164 | descriptor_t *gdt_p = (descriptor_t *) gdtr.base; |
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165 | |||
1816 | decky | 166 | // gdtr_load(&gdtr); |
1810 | decky | 167 | |
1829 | decky | 168 | if (config.cpu_active == 1) { |
169 | traps_init(); |
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170 | xen_set_trap_table(traps); |
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171 | /* |
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172 | * NOTE: bootstrap CPU has statically allocated TSS, because |
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173 | * the heap hasn't been initialized so far. |
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174 | */ |
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1810 | decky | 175 | tss_p = &tss; |
1829 | decky | 176 | } else { |
177 | tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
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178 | if (!tss_p) |
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179 | panic("could not allocate TSS\n"); |
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180 | } |
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1810 | decky | 181 | |
1816 | decky | 182 | // tss_initialize(tss_p); |
1810 | decky | 183 | |
184 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
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185 | gdt_p[TSS_DES].special = 1; |
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186 | gdt_p[TSS_DES].granularity = 0; |
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187 | |||
188 | gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); |
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189 | gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); |
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190 | |||
191 | /* |
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192 | * As of this moment, the current CPU has its own GDT pointing |
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193 | * to its own TSS. We just need to load the TR register. |
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194 | */ |
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1816 | decky | 195 | // tr_load(selector(TSS_DES)); |
1810 | decky | 196 | |
197 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
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198 | clean_AM_flag(); /* Disable alignment check */ |
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199 | } |
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200 | |||
201 | void set_tls_desc(uintptr_t tls) |
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202 | { |
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203 | ptr_16_32_t cpugdtr; |
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204 | descriptor_t *gdt_p; |
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205 | |||
206 | gdtr_store(&cpugdtr); |
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207 | gdt_p = (descriptor_t *) cpugdtr.base; |
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208 | gdt_setbase(&gdt_p[TLS_DES], tls); |
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209 | /* Reload gdt register to update GS in CPU */ |
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210 | gdtr_load(&cpugdtr); |
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211 | } |
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212 | |||
213 | /** @} |
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214 | */ |