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1 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2001-2004 Jakub Jermar |
1 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1888 | jermar | 29 | /** @addtogroup ia32 |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
1 | jermar | 35 | #include <arch/types.h> |
11 | jermar | 36 | #include <arch/smp/apic.h> |
37 | #include <arch/smp/ap.h> |
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34 | jermar | 38 | #include <arch/smp/mps.h> |
693 | decky | 39 | #include <arch/boot/boot.h> |
1 | jermar | 40 | #include <mm/page.h> |
41 | #include <time/delay.h> |
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576 | palkovsky | 42 | #include <interrupt.h> |
1 | jermar | 43 | #include <arch/interrupt.h> |
44 | #include <print.h> |
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45 | #include <arch/asm.h> |
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46 | #include <arch.h> |
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1970 | decky | 47 | #include <ddi/irq.h> |
48 | #include <ddi/device.h> |
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1 | jermar | 49 | |
458 | decky | 50 | #ifdef CONFIG_SMP |
16 | jermar | 51 | |
1 | jermar | 52 | /* |
512 | jermar | 53 | * Advanced Programmable Interrupt Controller for SMP systems. |
1 | jermar | 54 | * Tested on: |
750 | jermar | 55 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
523 | jermar | 56 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
516 | jermar | 57 | * VMware Workstation 5.5 with 2 CPUs |
812 | jermar | 58 | * QEMU 0.8.0 with 2-15 CPUs |
1 | jermar | 59 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
437 | decky | 60 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
61 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
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1 | jermar | 62 | */ |
63 | |||
64 | /* |
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65 | * These variables either stay configured as initilalized, or are changed by |
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66 | * the MP configuration code. |
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67 | * |
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68 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
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69 | * optimize the code too much and accesses to l_apic and io_apic, that must |
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70 | * always be 32-bit, would use byte oriented instructions. |
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71 | */ |
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1780 | jermar | 72 | volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; |
73 | volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; |
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1 | jermar | 74 | |
1780 | jermar | 75 | uint32_t apic_id_mask = 0; |
1970 | decky | 76 | static irq_t l_apic_timer_irq; |
1 | jermar | 77 | |
514 | jermar | 78 | static int apic_poll_errors(void); |
1 | jermar | 79 | |
515 | jermar | 80 | #ifdef LAPIC_VERBOSE |
514 | jermar | 81 | static char *delmod_str[] = { |
82 | "Fixed", |
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83 | "Lowest Priority", |
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84 | "SMI", |
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85 | "Reserved", |
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86 | "NMI", |
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87 | "INIT", |
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88 | "STARTUP", |
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89 | "ExtInt" |
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90 | }; |
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91 | |||
92 | static char *destmod_str[] = { |
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93 | "Physical", |
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94 | "Logical" |
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95 | }; |
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96 | |||
97 | static char *trigmod_str[] = { |
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98 | "Edge", |
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99 | "Level" |
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100 | }; |
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101 | |||
102 | static char *mask_str[] = { |
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103 | "Unmasked", |
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104 | "Masked" |
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105 | }; |
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106 | |||
107 | static char *delivs_str[] = { |
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108 | "Idle", |
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109 | "Send Pending" |
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110 | }; |
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111 | |||
112 | static char *tm_mode_str[] = { |
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113 | "One-shot", |
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114 | "Periodic" |
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115 | }; |
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116 | |||
117 | static char *intpol_str[] = { |
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118 | "Polarity High", |
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119 | "Polarity Low" |
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120 | }; |
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515 | jermar | 121 | #endif /* LAPIC_VERBOSE */ |
514 | jermar | 122 | |
1970 | decky | 123 | /** APIC spurious interrupt handler. |
124 | * |
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125 | * @param n Interrupt vector. |
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126 | * @param istate Interrupted state. |
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127 | */ |
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128 | static void apic_spurious(int n, istate_t *istate) |
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129 | { |
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130 | #ifdef CONFIG_DEBUG |
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131 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
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132 | #endif |
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133 | } |
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576 | palkovsky | 134 | |
1970 | decky | 135 | static irq_ownership_t l_apic_timer_claim(void) |
136 | { |
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137 | return IRQ_ACCEPT; |
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138 | } |
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576 | palkovsky | 139 | |
1970 | decky | 140 | static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...) |
141 | { |
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142 | clock(); |
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143 | } |
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144 | |||
513 | jermar | 145 | /** Initialize APIC on BSP. */ |
1 | jermar | 146 | void apic_init(void) |
147 | { |
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515 | jermar | 148 | io_apic_id_t idreg; |
2101 | decky | 149 | unsigned int i; |
1 | jermar | 150 | |
958 | jermar | 151 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
1 | jermar | 152 | |
153 | enable_irqs_function = io_apic_enable_irqs; |
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154 | disable_irqs_function = io_apic_disable_irqs; |
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155 | eoi_function = l_apic_eoi; |
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156 | |||
157 | /* |
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158 | * Configure interrupt routing. |
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159 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
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160 | * Other interrupts will be forwarded to the lowest priority CPU. |
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161 | */ |
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162 | io_apic_disable_irqs(0xffff); |
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1970 | decky | 163 | |
164 | irq_initialize(&l_apic_timer_irq); |
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165 | l_apic_timer_irq.devno = device_assign_devno(); |
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166 | l_apic_timer_irq.inr = IRQ_CLK; |
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167 | l_apic_timer_irq.claim = l_apic_timer_claim; |
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168 | l_apic_timer_irq.handler = l_apic_timer_irq_handler; |
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169 | irq_register(&l_apic_timer_irq); |
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170 | |||
515 | jermar | 171 | for (i = 0; i < IRQ_COUNT; i++) { |
1 | jermar | 172 | int pin; |
173 | |||
1970 | decky | 174 | if ((pin = smp_irq_to_pin(i)) != -1) |
2101 | decky | 175 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI); |
1 | jermar | 176 | } |
177 | |||
178 | /* |
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179 | * Ensure that io_apic has unique ID. |
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180 | */ |
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515 | jermar | 181 | idreg.value = io_apic_read(IOAPICID); |
1970 | decky | 182 | if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
515 | jermar | 183 | for (i = 0; i < APIC_ID_COUNT; i++) { |
1970 | decky | 184 | if (!((1 << i) & apic_id_mask)) { |
515 | jermar | 185 | idreg.apic_id = i; |
186 | io_apic_write(IOAPICID, idreg.value); |
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1 | jermar | 187 | break; |
188 | } |
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189 | } |
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190 | } |
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191 | |||
192 | /* |
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193 | * Configure the BSP's lapic. |
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194 | */ |
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195 | l_apic_init(); |
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515 | jermar | 196 | |
1 | jermar | 197 | l_apic_debug(); |
198 | } |
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199 | |||
514 | jermar | 200 | /** Poll for APIC errors. |
201 | * |
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202 | * Examine Error Status Register and report all errors found. |
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203 | * |
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204 | * @return 0 on error, 1 on success. |
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205 | */ |
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1 | jermar | 206 | int apic_poll_errors(void) |
207 | { |
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514 | jermar | 208 | esr_t esr; |
1 | jermar | 209 | |
514 | jermar | 210 | esr.value = l_apic[ESR]; |
1 | jermar | 211 | |
514 | jermar | 212 | if (esr.send_checksum_error) |
515 | jermar | 213 | printf("Send Checksum Error\n"); |
514 | jermar | 214 | if (esr.receive_checksum_error) |
515 | jermar | 215 | printf("Receive Checksum Error\n"); |
514 | jermar | 216 | if (esr.send_accept_error) |
1 | jermar | 217 | printf("Send Accept Error\n"); |
514 | jermar | 218 | if (esr.receive_accept_error) |
1 | jermar | 219 | printf("Receive Accept Error\n"); |
514 | jermar | 220 | if (esr.send_illegal_vector) |
1 | jermar | 221 | printf("Send Illegal Vector\n"); |
514 | jermar | 222 | if (esr.received_illegal_vector) |
1 | jermar | 223 | printf("Received Illegal Vector\n"); |
514 | jermar | 224 | if (esr.illegal_register_address) |
1 | jermar | 225 | printf("Illegal Register Address\n"); |
125 | jermar | 226 | |
514 | jermar | 227 | return !esr.err_bitmap; |
1 | jermar | 228 | } |
229 | |||
514 | jermar | 230 | /** Send all CPUs excluding CPU IPI vector. |
231 | * |
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232 | * @param vector Interrupt vector to be sent. |
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233 | * |
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234 | * @return 0 on failure, 1 on success. |
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5 | jermar | 235 | */ |
1780 | jermar | 236 | int l_apic_broadcast_custom_ipi(uint8_t vector) |
5 | jermar | 237 | { |
513 | jermar | 238 | icr_t icr; |
5 | jermar | 239 | |
513 | jermar | 240 | icr.lo = l_apic[ICRlo]; |
241 | icr.delmod = DELMOD_FIXED; |
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242 | icr.destmod = DESTMOD_LOGIC; |
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243 | icr.level = LEVEL_ASSERT; |
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244 | icr.shorthand = SHORTHAND_ALL_EXCL; |
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245 | icr.trigger_mode = TRIGMOD_LEVEL; |
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246 | icr.vector = vector; |
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5 | jermar | 247 | |
513 | jermar | 248 | l_apic[ICRlo] = icr.lo; |
5 | jermar | 249 | |
513 | jermar | 250 | icr.lo = l_apic[ICRlo]; |
1684 | jermar | 251 | if (icr.delivs == DELIVS_PENDING) { |
252 | #ifdef CONFIG_DEBUG |
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5 | jermar | 253 | printf("IPI is pending.\n"); |
1684 | jermar | 254 | #endif |
255 | } |
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5 | jermar | 256 | |
257 | return apic_poll_errors(); |
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258 | } |
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259 | |||
514 | jermar | 260 | /** Universal Start-up Algorithm for bringing up the AP processors. |
261 | * |
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262 | * @param apicid APIC ID of the processor to be brought up. |
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263 | * |
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264 | * @return 0 on failure, 1 on success. |
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1 | jermar | 265 | */ |
1780 | jermar | 266 | int l_apic_send_init_ipi(uint8_t apicid) |
1 | jermar | 267 | { |
513 | jermar | 268 | icr_t icr; |
1 | jermar | 269 | int i; |
270 | |||
271 | /* |
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272 | * Read the ICR register in and zero all non-reserved fields. |
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273 | */ |
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513 | jermar | 274 | icr.lo = l_apic[ICRlo]; |
275 | icr.hi = l_apic[ICRhi]; |
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1 | jermar | 276 | |
513 | jermar | 277 | icr.delmod = DELMOD_INIT; |
278 | icr.destmod = DESTMOD_PHYS; |
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279 | icr.level = LEVEL_ASSERT; |
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280 | icr.trigger_mode = TRIGMOD_LEVEL; |
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281 | icr.shorthand = SHORTHAND_NONE; |
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282 | icr.vector = 0; |
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283 | icr.dest = apicid; |
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1 | jermar | 284 | |
513 | jermar | 285 | l_apic[ICRhi] = icr.hi; |
286 | l_apic[ICRlo] = icr.lo; |
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27 | jermar | 287 | |
1 | jermar | 288 | /* |
289 | * According to MP Specification, 20us should be enough to |
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290 | * deliver the IPI. |
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291 | */ |
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292 | delay(20); |
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293 | |||
1684 | jermar | 294 | if (!apic_poll_errors()) |
295 | return 0; |
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1 | jermar | 296 | |
513 | jermar | 297 | icr.lo = l_apic[ICRlo]; |
1684 | jermar | 298 | if (icr.delivs == DELIVS_PENDING) { |
299 | #ifdef CONFIG_DEBUG |
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1 | jermar | 300 | printf("IPI is pending.\n"); |
1684 | jermar | 301 | #endif |
302 | } |
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27 | jermar | 303 | |
513 | jermar | 304 | icr.delmod = DELMOD_INIT; |
305 | icr.destmod = DESTMOD_PHYS; |
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306 | icr.level = LEVEL_DEASSERT; |
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307 | icr.shorthand = SHORTHAND_NONE; |
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308 | icr.trigger_mode = TRIGMOD_LEVEL; |
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309 | icr.vector = 0; |
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310 | l_apic[ICRlo] = icr.lo; |
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1 | jermar | 311 | |
312 | /* |
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313 | * Wait 10ms as MP Specification specifies. |
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314 | */ |
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315 | delay(10000); |
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316 | |||
27 | jermar | 317 | if (!is_82489DX_apic(l_apic[LAVR])) { |
318 | /* |
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319 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
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320 | */ |
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321 | for (i = 0; i<2; i++) { |
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513 | jermar | 322 | icr.lo = l_apic[ICRlo]; |
1780 | jermar | 323 | icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */ |
513 | jermar | 324 | icr.delmod = DELMOD_STARTUP; |
325 | icr.destmod = DESTMOD_PHYS; |
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326 | icr.level = LEVEL_ASSERT; |
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327 | icr.shorthand = SHORTHAND_NONE; |
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328 | icr.trigger_mode = TRIGMOD_LEVEL; |
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329 | l_apic[ICRlo] = icr.lo; |
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27 | jermar | 330 | delay(200); |
331 | } |
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1 | jermar | 332 | } |
333 | |||
334 | return apic_poll_errors(); |
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335 | } |
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336 | |||
514 | jermar | 337 | /** Initialize Local APIC. */ |
1 | jermar | 338 | void l_apic_init(void) |
339 | { |
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513 | jermar | 340 | lvt_error_t error; |
341 | lvt_lint_t lint; |
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750 | jermar | 342 | tpr_t tpr; |
513 | jermar | 343 | svr_t svr; |
514 | jermar | 344 | icr_t icr; |
345 | tdcr_t tdcr; |
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513 | jermar | 346 | lvt_tm_t tm; |
672 | jermar | 347 | ldr_t ldr; |
348 | dfr_t dfr; |
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1780 | jermar | 349 | uint32_t t1, t2; |
1 | jermar | 350 | |
513 | jermar | 351 | /* Initialize LVT Error register. */ |
352 | error.value = l_apic[LVT_Err]; |
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353 | error.masked = true; |
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354 | l_apic[LVT_Err] = error.value; |
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1 | jermar | 355 | |
513 | jermar | 356 | /* Initialize LVT LINT0 register. */ |
357 | lint.value = l_apic[LVT_LINT0]; |
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358 | lint.masked = true; |
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359 | l_apic[LVT_LINT0] = lint.value; |
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1 | jermar | 360 | |
513 | jermar | 361 | /* Initialize LVT LINT1 register. */ |
362 | lint.value = l_apic[LVT_LINT1]; |
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363 | lint.masked = true; |
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364 | l_apic[LVT_LINT1] = lint.value; |
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750 | jermar | 365 | |
366 | /* Task Priority Register initialization. */ |
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367 | tpr.value = l_apic[TPR]; |
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368 | tpr.pri_sc = 0; |
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369 | tpr.pri = 0; |
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370 | l_apic[TPR] = tpr.value; |
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513 | jermar | 371 | |
372 | /* Spurious-Interrupt Vector Register initialization. */ |
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373 | svr.value = l_apic[SVR]; |
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374 | svr.vector = VECTOR_APIC_SPUR; |
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375 | svr.lapic_enabled = true; |
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750 | jermar | 376 | svr.focus_checking = true; |
513 | jermar | 377 | l_apic[SVR] = svr.value; |
378 | |||
31 | jermar | 379 | if (CPU->arch.family >= 6) |
380 | enable_l_apic_in_msr(); |
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1 | jermar | 381 | |
513 | jermar | 382 | /* Interrupt Command Register initialization. */ |
383 | icr.lo = l_apic[ICRlo]; |
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384 | icr.delmod = DELMOD_INIT; |
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385 | icr.destmod = DESTMOD_PHYS; |
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386 | icr.level = LEVEL_DEASSERT; |
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387 | icr.shorthand = SHORTHAND_ALL_INCL; |
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388 | icr.trigger_mode = TRIGMOD_LEVEL; |
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389 | l_apic[ICRlo] = icr.lo; |
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1 | jermar | 390 | |
514 | jermar | 391 | /* Timer Divide Configuration Register initialization. */ |
392 | tdcr.value = l_apic[TDCR]; |
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393 | tdcr.div_value = DIVIDE_1; |
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394 | l_apic[TDCR] = tdcr.value; |
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1 | jermar | 395 | |
514 | jermar | 396 | /* Program local timer. */ |
513 | jermar | 397 | tm.value = l_apic[LVT_Tm]; |
398 | tm.vector = VECTOR_CLK; |
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399 | tm.mode = TIMER_PERIODIC; |
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400 | tm.masked = false; |
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401 | l_apic[LVT_Tm] = tm.value; |
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402 | |||
1540 | jermar | 403 | /* |
404 | * Measure and configure the timer to generate timer |
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405 | * interrupt with period 1s/HZ seconds. |
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406 | */ |
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1 | jermar | 407 | t1 = l_apic[CCRT]; |
408 | l_apic[ICRT] = 0xffffffff; |
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409 | |||
410 | while (l_apic[CCRT] == t1) |
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411 | ; |
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412 | |||
413 | t1 = l_apic[CCRT]; |
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1540 | jermar | 414 | delay(1000000/HZ); |
1 | jermar | 415 | t2 = l_apic[CCRT]; |
416 | |||
417 | l_apic[ICRT] = t1-t2; |
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672 | jermar | 418 | |
419 | /* Program Logical Destination Register. */ |
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420 | ldr.value = l_apic[LDR]; |
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421 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
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422 | ldr.id = (1<<CPU->id); |
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423 | l_apic[LDR] = ldr.value; |
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424 | |||
425 | /* Program Destination Format Register for Flat mode. */ |
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426 | dfr.value = l_apic[DFR]; |
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427 | dfr.model = MODEL_FLAT; |
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428 | l_apic[DFR] = dfr.value; |
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1 | jermar | 429 | } |
430 | |||
514 | jermar | 431 | /** Local APIC End of Interrupt. */ |
1 | jermar | 432 | void l_apic_eoi(void) |
433 | { |
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434 | l_apic[EOI] = 0; |
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435 | } |
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436 | |||
514 | jermar | 437 | /** Dump content of Local APIC registers. */ |
1 | jermar | 438 | void l_apic_debug(void) |
439 | { |
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440 | #ifdef LAPIC_VERBOSE |
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514 | jermar | 441 | lvt_tm_t tm; |
442 | lvt_lint_t lint; |
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443 | lvt_error_t error; |
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444 | |||
16 | jermar | 445 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
1 | jermar | 446 | |
514 | jermar | 447 | tm.value = l_apic[LVT_Tm]; |
1196 | cejka | 448 | printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
514 | jermar | 449 | lint.value = l_apic[LVT_LINT0]; |
1196 | cejka | 450 | printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
514 | jermar | 451 | lint.value = l_apic[LVT_LINT1]; |
1196 | cejka | 452 | printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
514 | jermar | 453 | error.value = l_apic[LVT_Err]; |
1196 | cejka | 454 | printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
1 | jermar | 455 | #endif |
456 | } |
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457 | |||
514 | jermar | 458 | /** Get Local APIC ID. |
459 | * |
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460 | * @return Local APIC ID. |
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461 | */ |
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1780 | jermar | 462 | uint8_t l_apic_id(void) |
16 | jermar | 463 | { |
515 | jermar | 464 | l_apic_id_t idreg; |
514 | jermar | 465 | |
515 | jermar | 466 | idreg.value = l_apic[L_APIC_ID]; |
467 | return idreg.apic_id; |
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16 | jermar | 468 | } |
469 | |||
514 | jermar | 470 | /** Read from IO APIC register. |
471 | * |
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472 | * @param address IO APIC register address. |
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473 | * |
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474 | * @return Content of the addressed IO APIC register. |
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475 | */ |
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1780 | jermar | 476 | uint32_t io_apic_read(uint8_t address) |
1 | jermar | 477 | { |
514 | jermar | 478 | io_regsel_t regsel; |
1 | jermar | 479 | |
514 | jermar | 480 | regsel.value = io_apic[IOREGSEL]; |
481 | regsel.reg_addr = address; |
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482 | io_apic[IOREGSEL] = regsel.value; |
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1 | jermar | 483 | return io_apic[IOWIN]; |
484 | } |
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485 | |||
514 | jermar | 486 | /** Write to IO APIC register. |
487 | * |
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488 | * @param address IO APIC register address. |
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1708 | jermar | 489 | * @param x Content to be written to the addressed IO APIC register. |
514 | jermar | 490 | */ |
1780 | jermar | 491 | void io_apic_write(uint8_t address, uint32_t x) |
1 | jermar | 492 | { |
514 | jermar | 493 | io_regsel_t regsel; |
494 | |||
495 | regsel.value = io_apic[IOREGSEL]; |
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496 | regsel.reg_addr = address; |
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497 | io_apic[IOREGSEL] = regsel.value; |
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1 | jermar | 498 | io_apic[IOWIN] = x; |
499 | } |
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500 | |||
514 | jermar | 501 | /** Change some attributes of one item in I/O Redirection Table. |
502 | * |
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503 | * @param pin IO APIC pin number. |
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504 | * @param dest Interrupt destination address. |
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505 | * @param v Interrupt vector to trigger. |
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506 | * @param flags Flags. |
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507 | */ |
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1780 | jermar | 508 | void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags) |
1 | jermar | 509 | { |
512 | jermar | 510 | io_redirection_reg_t reg; |
514 | jermar | 511 | int dlvr = DELMOD_FIXED; |
1 | jermar | 512 | |
513 | if (flags & LOPRI) |
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512 | jermar | 514 | dlvr = DELMOD_LOWPRI; |
515 | |||
514 | jermar | 516 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
517 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
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1 | jermar | 518 | |
672 | jermar | 519 | reg.dest = dest; |
512 | jermar | 520 | reg.destmod = DESTMOD_LOGIC; |
521 | reg.trigger_mode = TRIGMOD_EDGE; |
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522 | reg.intpol = POLARITY_HIGH; |
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523 | reg.delmod = dlvr; |
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524 | reg.intvec = v; |
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1 | jermar | 525 | |
514 | jermar | 526 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
527 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
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1 | jermar | 528 | } |
529 | |||
514 | jermar | 530 | /** Mask IRQs in IO APIC. |
531 | * |
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532 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
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533 | */ |
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1780 | jermar | 534 | void io_apic_disable_irqs(uint16_t irqmask) |
1 | jermar | 535 | { |
512 | jermar | 536 | io_redirection_reg_t reg; |
2101 | decky | 537 | unsigned int i; |
538 | int pin; |
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1 | jermar | 539 | |
2101 | decky | 540 | for (i = 0; i < 16; i++) { |
541 | if (irqmask & (1 << i)) { |
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1 | jermar | 542 | /* |
543 | * Mask the signal input in IO APIC if there is a |
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544 | * mapping for the respective IRQ number. |
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545 | */ |
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512 | jermar | 546 | pin = smp_irq_to_pin(i); |
1 | jermar | 547 | if (pin != -1) { |
2101 | decky | 548 | reg.lo = io_apic_read(IOREDTBL + pin * 2); |
512 | jermar | 549 | reg.masked = true; |
2101 | decky | 550 | io_apic_write(IOREDTBL + pin * 2, reg.lo); |
1 | jermar | 551 | } |
552 | |||
553 | } |
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554 | } |
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555 | } |
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556 | |||
514 | jermar | 557 | /** Unmask IRQs in IO APIC. |
558 | * |
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559 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
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560 | */ |
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1780 | jermar | 561 | void io_apic_enable_irqs(uint16_t irqmask) |
1 | jermar | 562 | { |
2101 | decky | 563 | unsigned int i; |
564 | int pin; |
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512 | jermar | 565 | io_redirection_reg_t reg; |
1 | jermar | 566 | |
2101 | decky | 567 | for (i = 0;i < 16; i++) { |
568 | if (irqmask & (1 << i)) { |
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1 | jermar | 569 | /* |
570 | * Unmask the signal input in IO APIC if there is a |
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571 | * mapping for the respective IRQ number. |
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572 | */ |
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512 | jermar | 573 | pin = smp_irq_to_pin(i); |
1 | jermar | 574 | if (pin != -1) { |
2101 | decky | 575 | reg.lo = io_apic_read(IOREDTBL + pin * 2); |
512 | jermar | 576 | reg.masked = false; |
2101 | decky | 577 | io_apic_write(IOREDTBL + pin * 2, reg.lo); |
1 | jermar | 578 | } |
579 | |||
580 | } |
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581 | } |
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582 | } |
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583 | |||
458 | decky | 584 | #endif /* CONFIG_SMP */ |
1702 | cejka | 585 | |
1888 | jermar | 586 | /** @} |
1702 | cejka | 587 | */ |