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2292 | hudecek | 1 | /* |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup ia32 |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
35 | #include <arch/types.h> |
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36 | #include <arch/smp/apic.h> |
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37 | #include <arch/smp/ap.h> |
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38 | #include <arch/smp/mps.h> |
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39 | #include <arch/boot/boot.h> |
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40 | #include <mm/page.h> |
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41 | #include <time/delay.h> |
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42 | #include <interrupt.h> |
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43 | #include <arch/interrupt.h> |
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44 | #include <print.h> |
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45 | #include <arch/asm.h> |
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46 | #include <arch.h> |
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47 | #include <ddi/irq.h> |
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48 | #include <ddi/device.h> |
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49 | |||
50 | #ifdef CONFIG_SMP |
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51 | |||
52 | /* |
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53 | * Advanced Programmable Interrupt Controller for SMP systems. |
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54 | * Tested on: |
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55 | * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs |
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56 | * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs |
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57 | * VMware Workstation 5.5 with 2 CPUs |
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58 | * QEMU 0.8.0 with 2-15 CPUs |
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59 | * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs |
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60 | * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs |
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61 | * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs |
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62 | */ |
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63 | |||
64 | /* |
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65 | * These variables either stay configured as initilalized, or are changed by |
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66 | * the MP configuration code. |
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67 | * |
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68 | * Pay special attention to the volatile keyword. Without it, gcc -O2 would |
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69 | * optimize the code too much and accesses to l_apic and io_apic, that must |
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70 | * always be 32-bit, would use byte oriented instructions. |
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71 | */ |
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72 | volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; |
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73 | volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; |
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74 | |||
75 | uint32_t apic_id_mask = 0; |
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76 | static irq_t l_apic_timer_irq; |
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77 | |||
78 | static int apic_poll_errors(void); |
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79 | |||
80 | #ifdef LAPIC_VERBOSE |
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81 | static char *delmod_str[] = { |
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82 | "Fixed", |
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83 | "Lowest Priority", |
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84 | "SMI", |
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85 | "Reserved", |
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86 | "NMI", |
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87 | "INIT", |
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88 | "STARTUP", |
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89 | "ExtInt" |
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90 | }; |
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91 | |||
92 | static char *destmod_str[] = { |
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93 | "Physical", |
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94 | "Logical" |
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95 | }; |
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96 | |||
97 | static char *trigmod_str[] = { |
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98 | "Edge", |
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99 | "Level" |
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100 | }; |
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101 | |||
102 | static char *mask_str[] = { |
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103 | "Unmasked", |
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104 | "Masked" |
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105 | }; |
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106 | |||
107 | static char *delivs_str[] = { |
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108 | "Idle", |
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109 | "Send Pending" |
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110 | }; |
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111 | |||
112 | static char *tm_mode_str[] = { |
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113 | "One-shot", |
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114 | "Periodic" |
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115 | }; |
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116 | |||
117 | static char *intpol_str[] = { |
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118 | "Polarity High", |
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119 | "Polarity Low" |
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120 | }; |
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121 | #endif /* LAPIC_VERBOSE */ |
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122 | |||
123 | /** APIC spurious interrupt handler. |
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124 | * |
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125 | * @param n Interrupt vector. |
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126 | * @param istate Interrupted state. |
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127 | */ |
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128 | static void apic_spurious(int n, istate_t *istate) |
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129 | { |
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130 | #ifdef CONFIG_DEBUG |
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131 | printf("cpu%d: APIC spurious interrupt\n", CPU->id); |
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132 | #endif |
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133 | } |
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134 | |||
135 | static irq_ownership_t l_apic_timer_claim(void) |
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136 | { |
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137 | return IRQ_ACCEPT; |
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138 | } |
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139 | |||
140 | static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...) |
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141 | { |
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2307 | hudecek | 142 | /* |
143 | * Holding a spinlock could prevent clock() from preempting |
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144 | * the current thread. In this case, we don't need to hold the |
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145 | * irq->lock so we just unlock it and then lock it again. |
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146 | */ |
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147 | spinlock_unlock(&irq->lock); |
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2292 | hudecek | 148 | clock(); |
2307 | hudecek | 149 | spinlock_lock(&irq->lock); |
2292 | hudecek | 150 | } |
151 | |||
152 | /** Initialize APIC on BSP. */ |
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153 | void apic_init(void) |
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154 | { |
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155 | io_apic_id_t idreg; |
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156 | unsigned int i; |
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157 | |||
158 | exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious); |
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159 | |||
160 | enable_irqs_function = io_apic_enable_irqs; |
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161 | disable_irqs_function = io_apic_disable_irqs; |
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162 | eoi_function = l_apic_eoi; |
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163 | |||
164 | /* |
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165 | * Configure interrupt routing. |
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166 | * IRQ 0 remains masked as the time signal is generated by l_apic's themselves. |
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167 | * Other interrupts will be forwarded to the lowest priority CPU. |
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168 | */ |
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169 | io_apic_disable_irqs(0xffff); |
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170 | |||
171 | irq_initialize(&l_apic_timer_irq); |
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2307 | hudecek | 172 | l_apic_timer_irq.preack = true; |
2292 | hudecek | 173 | l_apic_timer_irq.devno = device_assign_devno(); |
174 | l_apic_timer_irq.inr = IRQ_CLK; |
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175 | l_apic_timer_irq.claim = l_apic_timer_claim; |
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176 | l_apic_timer_irq.handler = l_apic_timer_irq_handler; |
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177 | irq_register(&l_apic_timer_irq); |
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178 | |||
179 | for (i = 0; i < IRQ_COUNT; i++) { |
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180 | int pin; |
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181 | |||
182 | if ((pin = smp_irq_to_pin(i)) != -1) |
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183 | io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI); |
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184 | } |
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185 | |||
186 | /* |
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187 | * Ensure that io_apic has unique ID. |
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188 | */ |
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189 | idreg.value = io_apic_read(IOAPICID); |
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190 | if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */ |
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191 | for (i = 0; i < APIC_ID_COUNT; i++) { |
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192 | if (!((1 << i) & apic_id_mask)) { |
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193 | idreg.apic_id = i; |
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194 | io_apic_write(IOAPICID, idreg.value); |
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195 | break; |
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196 | } |
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197 | } |
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198 | } |
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199 | |||
200 | /* |
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201 | * Configure the BSP's lapic. |
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202 | */ |
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203 | l_apic_init(); |
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204 | |||
205 | l_apic_debug(); |
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206 | } |
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207 | |||
208 | /** Poll for APIC errors. |
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209 | * |
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210 | * Examine Error Status Register and report all errors found. |
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211 | * |
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212 | * @return 0 on error, 1 on success. |
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213 | */ |
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214 | int apic_poll_errors(void) |
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215 | { |
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216 | esr_t esr; |
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217 | |||
218 | esr.value = l_apic[ESR]; |
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219 | |||
220 | if (esr.send_checksum_error) |
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221 | printf("Send Checksum Error\n"); |
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222 | if (esr.receive_checksum_error) |
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223 | printf("Receive Checksum Error\n"); |
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224 | if (esr.send_accept_error) |
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225 | printf("Send Accept Error\n"); |
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226 | if (esr.receive_accept_error) |
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227 | printf("Receive Accept Error\n"); |
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228 | if (esr.send_illegal_vector) |
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229 | printf("Send Illegal Vector\n"); |
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230 | if (esr.received_illegal_vector) |
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231 | printf("Received Illegal Vector\n"); |
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232 | if (esr.illegal_register_address) |
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233 | printf("Illegal Register Address\n"); |
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234 | |||
235 | return !esr.err_bitmap; |
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236 | } |
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237 | |||
238 | /** Send all CPUs excluding CPU IPI vector. |
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239 | * |
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240 | * @param vector Interrupt vector to be sent. |
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241 | * |
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242 | * @return 0 on failure, 1 on success. |
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243 | */ |
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244 | int l_apic_broadcast_custom_ipi(uint8_t vector) |
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245 | { |
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246 | icr_t icr; |
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247 | |||
248 | icr.lo = l_apic[ICRlo]; |
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249 | icr.delmod = DELMOD_FIXED; |
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250 | icr.destmod = DESTMOD_LOGIC; |
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251 | icr.level = LEVEL_ASSERT; |
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252 | icr.shorthand = SHORTHAND_ALL_EXCL; |
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253 | icr.trigger_mode = TRIGMOD_LEVEL; |
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254 | icr.vector = vector; |
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255 | |||
256 | l_apic[ICRlo] = icr.lo; |
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257 | |||
258 | icr.lo = l_apic[ICRlo]; |
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259 | if (icr.delivs == DELIVS_PENDING) { |
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260 | #ifdef CONFIG_DEBUG |
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261 | printf("IPI is pending.\n"); |
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262 | #endif |
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263 | } |
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264 | |||
265 | return apic_poll_errors(); |
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266 | } |
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267 | |||
268 | /** Universal Start-up Algorithm for bringing up the AP processors. |
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269 | * |
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270 | * @param apicid APIC ID of the processor to be brought up. |
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271 | * |
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272 | * @return 0 on failure, 1 on success. |
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273 | */ |
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274 | int l_apic_send_init_ipi(uint8_t apicid) |
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275 | { |
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276 | icr_t icr; |
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277 | int i; |
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278 | |||
279 | /* |
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280 | * Read the ICR register in and zero all non-reserved fields. |
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281 | */ |
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282 | icr.lo = l_apic[ICRlo]; |
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283 | icr.hi = l_apic[ICRhi]; |
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284 | |||
285 | icr.delmod = DELMOD_INIT; |
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286 | icr.destmod = DESTMOD_PHYS; |
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287 | icr.level = LEVEL_ASSERT; |
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288 | icr.trigger_mode = TRIGMOD_LEVEL; |
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289 | icr.shorthand = SHORTHAND_NONE; |
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290 | icr.vector = 0; |
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291 | icr.dest = apicid; |
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292 | |||
293 | l_apic[ICRhi] = icr.hi; |
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294 | l_apic[ICRlo] = icr.lo; |
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295 | |||
296 | /* |
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297 | * According to MP Specification, 20us should be enough to |
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298 | * deliver the IPI. |
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299 | */ |
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300 | delay(20); |
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301 | |||
302 | if (!apic_poll_errors()) |
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303 | return 0; |
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304 | |||
305 | icr.lo = l_apic[ICRlo]; |
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306 | if (icr.delivs == DELIVS_PENDING) { |
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307 | #ifdef CONFIG_DEBUG |
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308 | printf("IPI is pending.\n"); |
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309 | #endif |
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310 | } |
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311 | |||
312 | icr.delmod = DELMOD_INIT; |
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313 | icr.destmod = DESTMOD_PHYS; |
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314 | icr.level = LEVEL_DEASSERT; |
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315 | icr.shorthand = SHORTHAND_NONE; |
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316 | icr.trigger_mode = TRIGMOD_LEVEL; |
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317 | icr.vector = 0; |
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318 | l_apic[ICRlo] = icr.lo; |
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319 | |||
320 | /* |
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321 | * Wait 10ms as MP Specification specifies. |
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322 | */ |
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323 | delay(10000); |
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324 | |||
325 | if (!is_82489DX_apic(l_apic[LAVR])) { |
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326 | /* |
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327 | * If this is not 82489DX-based l_apic we must send two STARTUP IPI's. |
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328 | */ |
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329 | for (i = 0; i<2; i++) { |
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330 | icr.lo = l_apic[ICRlo]; |
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331 | icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */ |
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332 | icr.delmod = DELMOD_STARTUP; |
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333 | icr.destmod = DESTMOD_PHYS; |
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334 | icr.level = LEVEL_ASSERT; |
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335 | icr.shorthand = SHORTHAND_NONE; |
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336 | icr.trigger_mode = TRIGMOD_LEVEL; |
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337 | l_apic[ICRlo] = icr.lo; |
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338 | delay(200); |
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339 | } |
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340 | } |
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341 | |||
342 | return apic_poll_errors(); |
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343 | } |
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344 | |||
345 | /** Initialize Local APIC. */ |
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346 | void l_apic_init(void) |
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347 | { |
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348 | lvt_error_t error; |
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349 | lvt_lint_t lint; |
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350 | tpr_t tpr; |
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351 | svr_t svr; |
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352 | icr_t icr; |
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353 | tdcr_t tdcr; |
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354 | lvt_tm_t tm; |
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355 | ldr_t ldr; |
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356 | dfr_t dfr; |
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357 | uint32_t t1, t2; |
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358 | |||
359 | /* Initialize LVT Error register. */ |
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360 | error.value = l_apic[LVT_Err]; |
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361 | error.masked = true; |
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362 | l_apic[LVT_Err] = error.value; |
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363 | |||
364 | /* Initialize LVT LINT0 register. */ |
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365 | lint.value = l_apic[LVT_LINT0]; |
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366 | lint.masked = true; |
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367 | l_apic[LVT_LINT0] = lint.value; |
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368 | |||
369 | /* Initialize LVT LINT1 register. */ |
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370 | lint.value = l_apic[LVT_LINT1]; |
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371 | lint.masked = true; |
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372 | l_apic[LVT_LINT1] = lint.value; |
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373 | |||
374 | /* Task Priority Register initialization. */ |
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375 | tpr.value = l_apic[TPR]; |
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376 | tpr.pri_sc = 0; |
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377 | tpr.pri = 0; |
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378 | l_apic[TPR] = tpr.value; |
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379 | |||
380 | /* Spurious-Interrupt Vector Register initialization. */ |
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381 | svr.value = l_apic[SVR]; |
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382 | svr.vector = VECTOR_APIC_SPUR; |
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383 | svr.lapic_enabled = true; |
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384 | svr.focus_checking = true; |
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385 | l_apic[SVR] = svr.value; |
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386 | |||
387 | if (CPU->arch.family >= 6) |
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388 | enable_l_apic_in_msr(); |
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389 | |||
390 | /* Interrupt Command Register initialization. */ |
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391 | icr.lo = l_apic[ICRlo]; |
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392 | icr.delmod = DELMOD_INIT; |
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393 | icr.destmod = DESTMOD_PHYS; |
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394 | icr.level = LEVEL_DEASSERT; |
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395 | icr.shorthand = SHORTHAND_ALL_INCL; |
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396 | icr.trigger_mode = TRIGMOD_LEVEL; |
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397 | l_apic[ICRlo] = icr.lo; |
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398 | |||
399 | /* Timer Divide Configuration Register initialization. */ |
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400 | tdcr.value = l_apic[TDCR]; |
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401 | tdcr.div_value = DIVIDE_1; |
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402 | l_apic[TDCR] = tdcr.value; |
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403 | |||
404 | /* Program local timer. */ |
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405 | tm.value = l_apic[LVT_Tm]; |
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406 | tm.vector = VECTOR_CLK; |
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407 | tm.mode = TIMER_PERIODIC; |
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408 | tm.masked = false; |
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409 | l_apic[LVT_Tm] = tm.value; |
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410 | |||
411 | /* |
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412 | * Measure and configure the timer to generate timer |
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413 | * interrupt with period 1s/HZ seconds. |
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414 | */ |
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415 | t1 = l_apic[CCRT]; |
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416 | l_apic[ICRT] = 0xffffffff; |
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417 | |||
418 | while (l_apic[CCRT] == t1) |
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419 | ; |
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420 | |||
421 | t1 = l_apic[CCRT]; |
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422 | delay(1000000/HZ); |
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423 | t2 = l_apic[CCRT]; |
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424 | |||
425 | l_apic[ICRT] = t1-t2; |
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426 | |||
427 | /* Program Logical Destination Register. */ |
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428 | ldr.value = l_apic[LDR]; |
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429 | if (CPU->id < sizeof(CPU->id)*8) /* size in bits */ |
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430 | ldr.id = (1<<CPU->id); |
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431 | l_apic[LDR] = ldr.value; |
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432 | |||
433 | /* Program Destination Format Register for Flat mode. */ |
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434 | dfr.value = l_apic[DFR]; |
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435 | dfr.model = MODEL_FLAT; |
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436 | l_apic[DFR] = dfr.value; |
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437 | } |
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438 | |||
439 | /** Local APIC End of Interrupt. */ |
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440 | void l_apic_eoi(void) |
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441 | { |
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442 | l_apic[EOI] = 0; |
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443 | } |
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444 | |||
445 | /** Dump content of Local APIC registers. */ |
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446 | void l_apic_debug(void) |
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447 | { |
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448 | #ifdef LAPIC_VERBOSE |
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449 | lvt_tm_t tm; |
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450 | lvt_lint_t lint; |
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451 | lvt_error_t error; |
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452 | |||
453 | printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id()); |
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454 | |||
455 | tm.value = l_apic[LVT_Tm]; |
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456 | printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); |
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457 | lint.value = l_apic[LVT_LINT0]; |
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458 | printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
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459 | lint.value = l_apic[LVT_LINT1]; |
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460 | printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); |
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461 | error.value = l_apic[LVT_Err]; |
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462 | printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]); |
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463 | #endif |
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464 | } |
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465 | |||
466 | /** Get Local APIC ID. |
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467 | * |
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468 | * @return Local APIC ID. |
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469 | */ |
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470 | uint8_t l_apic_id(void) |
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471 | { |
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472 | l_apic_id_t idreg; |
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473 | |||
474 | idreg.value = l_apic[L_APIC_ID]; |
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475 | return idreg.apic_id; |
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476 | } |
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477 | |||
478 | /** Read from IO APIC register. |
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479 | * |
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480 | * @param address IO APIC register address. |
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481 | * |
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482 | * @return Content of the addressed IO APIC register. |
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483 | */ |
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484 | uint32_t io_apic_read(uint8_t address) |
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485 | { |
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486 | io_regsel_t regsel; |
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487 | |||
488 | regsel.value = io_apic[IOREGSEL]; |
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489 | regsel.reg_addr = address; |
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490 | io_apic[IOREGSEL] = regsel.value; |
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491 | return io_apic[IOWIN]; |
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492 | } |
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493 | |||
494 | /** Write to IO APIC register. |
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495 | * |
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496 | * @param address IO APIC register address. |
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497 | * @param x Content to be written to the addressed IO APIC register. |
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498 | */ |
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499 | void io_apic_write(uint8_t address, uint32_t x) |
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500 | { |
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501 | io_regsel_t regsel; |
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502 | |||
503 | regsel.value = io_apic[IOREGSEL]; |
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504 | regsel.reg_addr = address; |
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505 | io_apic[IOREGSEL] = regsel.value; |
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506 | io_apic[IOWIN] = x; |
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507 | } |
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508 | |||
509 | /** Change some attributes of one item in I/O Redirection Table. |
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510 | * |
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511 | * @param pin IO APIC pin number. |
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512 | * @param dest Interrupt destination address. |
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513 | * @param v Interrupt vector to trigger. |
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514 | * @param flags Flags. |
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515 | */ |
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516 | void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags) |
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517 | { |
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518 | io_redirection_reg_t reg; |
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519 | int dlvr = DELMOD_FIXED; |
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520 | |||
521 | if (flags & LOPRI) |
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522 | dlvr = DELMOD_LOWPRI; |
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523 | |||
524 | reg.lo = io_apic_read(IOREDTBL + pin*2); |
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525 | reg.hi = io_apic_read(IOREDTBL + pin*2 + 1); |
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526 | |||
527 | reg.dest = dest; |
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528 | reg.destmod = DESTMOD_LOGIC; |
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529 | reg.trigger_mode = TRIGMOD_EDGE; |
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530 | reg.intpol = POLARITY_HIGH; |
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531 | reg.delmod = dlvr; |
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532 | reg.intvec = v; |
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533 | |||
534 | io_apic_write(IOREDTBL + pin*2, reg.lo); |
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535 | io_apic_write(IOREDTBL + pin*2 + 1, reg.hi); |
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536 | } |
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537 | |||
538 | /** Mask IRQs in IO APIC. |
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539 | * |
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540 | * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask). |
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541 | */ |
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542 | void io_apic_disable_irqs(uint16_t irqmask) |
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543 | { |
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544 | io_redirection_reg_t reg; |
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545 | unsigned int i; |
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546 | int pin; |
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547 | |||
548 | for (i = 0; i < 16; i++) { |
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549 | if (irqmask & (1 << i)) { |
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550 | /* |
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551 | * Mask the signal input in IO APIC if there is a |
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552 | * mapping for the respective IRQ number. |
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553 | */ |
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554 | pin = smp_irq_to_pin(i); |
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555 | if (pin != -1) { |
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556 | reg.lo = io_apic_read(IOREDTBL + pin * 2); |
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557 | reg.masked = true; |
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558 | io_apic_write(IOREDTBL + pin * 2, reg.lo); |
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559 | } |
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560 | |||
561 | } |
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562 | } |
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563 | } |
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564 | |||
565 | /** Unmask IRQs in IO APIC. |
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566 | * |
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567 | * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask). |
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568 | */ |
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569 | void io_apic_enable_irqs(uint16_t irqmask) |
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570 | { |
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571 | unsigned int i; |
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572 | int pin; |
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573 | io_redirection_reg_t reg; |
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574 | |||
575 | for (i = 0;i < 16; i++) { |
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576 | if (irqmask & (1 << i)) { |
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577 | /* |
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578 | * Unmask the signal input in IO APIC if there is a |
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579 | * mapping for the respective IRQ number. |
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580 | */ |
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581 | pin = smp_irq_to_pin(i); |
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582 | if (pin != -1) { |
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583 | reg.lo = io_apic_read(IOREDTBL + pin * 2); |
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584 | reg.masked = false; |
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585 | io_apic_write(IOREDTBL + pin * 2, reg.lo); |
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586 | } |
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587 | |||
588 | } |
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589 | } |
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590 | } |
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591 | |||
592 | #endif /* CONFIG_SMP */ |
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593 | |||
594 | /** @} |
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595 | */ |