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418 | jermar | 1 | # |
2 | # Copyright (C) 2005 Jakub Jermar |
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3 | # All rights reserved. |
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4 | # |
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5 | # Redistribution and use in source and binary forms, with or without |
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6 | # modification, are permitted provided that the following conditions |
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7 | # are met: |
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8 | # |
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9 | # - Redistributions of source code must retain the above copyright |
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10 | # notice, this list of conditions and the following disclaimer. |
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11 | # - Redistributions in binary form must reproduce the above copyright |
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12 | # notice, this list of conditions and the following disclaimer in the |
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13 | # documentation and/or other materials provided with the distribution. |
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14 | # - The name of the author may not be used to endorse or promote products |
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15 | # derived from this software without specific prior written permission. |
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16 | # |
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17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | # |
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28 | |||
1903 | jermar | 29 | #include <arch/arch.h> |
1789 | jermar | 30 | #include <arch/regdef.h> |
1823 | jermar | 31 | #include <arch/boot/boot.h> |
1917 | jermar | 32 | #include <arch/stack.h> |
846 | jermar | 33 | |
1823 | jermar | 34 | #include <arch/mm/mmu.h> |
35 | #include <arch/mm/tlb.h> |
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36 | #include <arch/mm/tte.h> |
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37 | |||
1903 | jermar | 38 | #ifdef CONFIG_SMP |
39 | #include <arch/context_offset.h> |
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40 | #endif |
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41 | |||
426 | jermar | 42 | .register %g2, #scratch |
43 | .register %g3, #scratch |
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44 | |||
418 | jermar | 45 | .section K_TEXT_START, "ax" |
46 | |||
1978 | jermar | 47 | #define BSP_FLAG 1 |
48 | |||
847 | jermar | 49 | /* |
1978 | jermar | 50 | * Here is where the kernel is passed control from the boot loader. |
1790 | jermar | 51 | * |
52 | * The registers are expected to be in this state: |
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1978 | jermar | 53 | * - %o0 starting address of physical memory + bootstrap processor flag |
54 | * bits 63...1: physical memory starting address / 2 |
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55 | * bit 0: non-zero on BSP processor, zero on AP processors |
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56 | * - %o1 bootinfo structure address (BSP only) |
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57 | * - %o2 bootinfo structure size (BSP only) |
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1792 | jermar | 58 | * |
1978 | jermar | 59 | * Moreover, we depend on boot having established the following environment: |
1792 | jermar | 60 | * - TLBs are on |
61 | * - identity mapping for the kernel image |
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847 | jermar | 62 | */ |
63 | |||
418 | jermar | 64 | .global kernel_image_start |
65 | kernel_image_start: |
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1978 | jermar | 66 | mov BSP_FLAG, %l0 |
67 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
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68 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
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846 | jermar | 69 | |
1978 | jermar | 70 | sethi %hi(physmem_base), %l5 |
71 | stx %l6, [%l5 + %lo(physmem_base)] |
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72 | |||
1790 | jermar | 73 | /* |
1978 | jermar | 74 | * Get bits 40:13 of physmem_base. |
75 | */ |
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76 | sethi %hi(mask_40_13), %l4 |
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77 | sethi %hi(physmem_base_40_13), %l3 |
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78 | ldx [%l4 + %lo(mask_40_13)], %l4 |
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79 | and %l6, %l4, %l5 ! l5 <= physmem_base[40:13] |
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80 | stx %l5, [%l3 + %lo(physmem_base_40_13)] |
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81 | |||
82 | /* |
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83 | * Prepare kernel 8K TLB data template. |
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84 | */ |
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85 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
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86 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
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87 | or %l3, %l5, %l3 |
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88 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
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89 | |||
90 | /* |
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1823 | jermar | 91 | * Setup basic runtime environment. |
1790 | jermar | 92 | */ |
424 | jermar | 93 | |
1954 | jermar | 94 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
1917 | jermar | 95 | wrpr %g0, 0, %canrestore ! get rid of windows we will never need again |
96 | wrpr %g0, 0, %otherwin ! make sure the window state is consistent |
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97 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel |
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1823 | jermar | 98 | |
1881 | jermar | 99 | wrpr %g0, 0, %tl ! TL = 0, primary context register is used |
1823 | jermar | 100 | |
1881 | jermar | 101 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking. |
1823 | jermar | 102 | |
1881 | jermar | 103 | wrpr %g0, 0, %pil ! intialize %pil |
104 | |||
1790 | jermar | 105 | /* |
1823 | jermar | 106 | * Switch to kernel trap table. |
107 | */ |
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1880 | jermar | 108 | sethi %hi(trap_table), %g1 |
109 | wrpr %g1, %lo(trap_table), %tba |
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1823 | jermar | 110 | |
111 | /* |
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112 | * Take over the DMMU by installing global locked |
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113 | * TTE entry identically mapping the first 4M |
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114 | * of memory. |
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1792 | jermar | 115 | * |
1823 | jermar | 116 | * In case of DMMU, no FLUSH instructions need to be |
117 | * issued. Because of that, the old DTLB contents can |
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118 | * be demapped pretty straightforwardly and without |
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119 | * causing any traps. |
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1792 | jermar | 120 | */ |
121 | |||
1823 | jermar | 122 | wr %g0, ASI_DMMU, %asi |
895 | jermar | 123 | |
1823 | jermar | 124 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
125 | set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1 |
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126 | |||
127 | ! demap context 0 |
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128 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
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129 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
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130 | membar #Sync |
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131 | |||
132 | #define SET_TLB_TAG(r1, context) \ |
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133 | set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
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134 | |||
135 | ! write DTLB tag |
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136 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
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137 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
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138 | membar #Sync |
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139 | |||
140 | #define SET_TLB_DATA(r1, r2, imm) \ |
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1887 | jermar | 141 | set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \ |
1978 | jermar | 142 | or %r1, %l5, %r1; \ |
143 | mov PAGESIZE_4M, %r2; \ |
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1823 | jermar | 144 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
145 | or %r1, %r2, %r1; \ |
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1880 | jermar | 146 | mov 1, %r2; \ |
1823 | jermar | 147 | sllx %r2, TTE_V_SHIFT, %r2; \ |
148 | or %r1, %r2, %r1; |
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149 | |||
150 | ! write DTLB data and install the kernel mapping |
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1887 | jermar | 151 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
1823 | jermar | 152 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
153 | membar #Sync |
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1868 | jermar | 154 | |
155 | /* |
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156 | * Because we cannot use global mappings (because we want to |
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157 | * have separate 64-bit address spaces for both the kernel |
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158 | * and the userspace), we prepare the identity mapping also in |
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159 | * context 1. This step is required by the |
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160 | * code installing the ITLB mapping. |
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161 | */ |
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162 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
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163 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
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164 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
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165 | membar #Sync |
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166 | |||
167 | ! write DTLB data and install the kernel mapping in context 1 |
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1887 | jermar | 168 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
1868 | jermar | 169 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
170 | membar #Sync |
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1823 | jermar | 171 | |
172 | /* |
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173 | * Now is time to take over the IMMU. |
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174 | * Unfortunatelly, it cannot be done as easily as the DMMU, |
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175 | * because the IMMU is mapping the code it executes. |
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176 | * |
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177 | * [ Note that brave experiments with disabling the IMMU |
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178 | * and using the DMMU approach failed after a dozen |
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179 | * of desparate days with only little success. ] |
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180 | * |
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181 | * The approach used here is inspired from OpenBSD. |
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182 | * First, the kernel creates IMMU mapping for itself |
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183 | * in context 1 (MEM_CONTEXT_TEMP) and switches to |
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184 | * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
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185 | * afterwards and replaced with the kernel permanent |
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186 | * mapping. Finally, the kernel switches back to |
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187 | * context 0 and demaps context 1. |
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188 | * |
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189 | * Moreover, the IMMU requires use of the FLUSH instructions. |
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190 | * But that is OK because we always use operands with |
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191 | * addresses already mapped by the taken over DTLB. |
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192 | */ |
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193 | |||
1852 | jermar | 194 | set kernel_image_start, %g5 |
1823 | jermar | 195 | |
196 | ! write ITLB tag of context 1 |
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197 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
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1880 | jermar | 198 | mov VA_DMMU_TAG_ACCESS, %g2 |
1823 | jermar | 199 | stxa %g1, [%g2] ASI_IMMU |
1852 | jermar | 200 | flush %g5 |
1823 | jermar | 201 | |
202 | ! write ITLB data and install the temporary mapping in context 1 |
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203 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
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204 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
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1852 | jermar | 205 | flush %g5 |
1823 | jermar | 206 | |
207 | ! switch to context 1 |
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1880 | jermar | 208 | mov MEM_CONTEXT_TEMP, %g1 |
1823 | jermar | 209 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
1852 | jermar | 210 | flush %g5 |
1823 | jermar | 211 | |
212 | ! demap context 0 |
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213 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
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214 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
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1852 | jermar | 215 | flush %g5 |
1823 | jermar | 216 | |
217 | ! write ITLB tag of context 0 |
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218 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
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1880 | jermar | 219 | mov VA_DMMU_TAG_ACCESS, %g2 |
1823 | jermar | 220 | stxa %g1, [%g2] ASI_IMMU |
1852 | jermar | 221 | flush %g5 |
1823 | jermar | 222 | |
223 | ! write ITLB data and install the permanent kernel mapping in context 0 |
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1887 | jermar | 224 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
1823 | jermar | 225 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
1852 | jermar | 226 | flush %g5 |
1823 | jermar | 227 | |
1906 | jermar | 228 | ! enter nucleus - using context 0 |
1823 | jermar | 229 | wrpr %g0, 1, %tl |
230 | |||
231 | ! demap context 1 |
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232 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
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233 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
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1852 | jermar | 234 | flush %g5 |
1823 | jermar | 235 | |
236 | ! set context 0 in the primary context register |
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237 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
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1852 | jermar | 238 | flush %g5 |
1823 | jermar | 239 | |
1906 | jermar | 240 | ! leave nucleus - using primary context, i.e. context 0 |
1823 | jermar | 241 | wrpr %g0, 0, %tl |
1864 | jermar | 242 | |
1903 | jermar | 243 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
244 | nop |
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1900 | jermar | 245 | |
1917 | jermar | 246 | /* |
247 | * So far, we have not touched the stack. |
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1975 | jermar | 248 | * It is a good idea to set the kernel stack to a known state now. |
1917 | jermar | 249 | */ |
250 | sethi %hi(temporary_boot_stack), %sp |
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251 | or %sp, %lo(temporary_boot_stack), %sp |
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252 | sub %sp, STACK_BIAS, %sp |
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253 | |||
1906 | jermar | 254 | sethi %hi(bootinfo), %o0 |
255 | call memcpy ! copy bootinfo |
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256 | or %o0, %lo(bootinfo), %o0 |
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257 | |||
1864 | jermar | 258 | call arch_pre_main |
259 | nop |
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1823 | jermar | 260 | |
426 | jermar | 261 | call main_bsp |
262 | nop |
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263 | |||
264 | /* Not reached. */ |
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265 | |||
1903 | jermar | 266 | 0: |
267 | ba 0b |
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268 | nop |
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269 | |||
270 | |||
271 | /* |
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272 | * Read MID from the processor. |
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273 | */ |
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274 | 1: |
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275 | ldxa [%g0] ASI_UPA_CONFIG, %g1 |
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276 | srlx %g1, UPA_CONFIG_MID_SHIFT, %g1 |
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277 | and %g1, UPA_CONFIG_MID_MASK, %g1 |
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278 | |||
1905 | jermar | 279 | #ifdef CONFIG_SMP |
1903 | jermar | 280 | /* |
281 | * Active loop for APs until the BSP picks them up. |
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282 | * A processor cannot leave the loop until the |
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283 | * global variable 'waking_up_mid' equals its |
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284 | * MID. |
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285 | */ |
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286 | set waking_up_mid, %g2 |
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424 | jermar | 287 | 2: |
1903 | jermar | 288 | ldx [%g2], %g3 |
289 | cmp %g3, %g1 |
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290 | bne 2b |
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424 | jermar | 291 | nop |
1903 | jermar | 292 | |
293 | /* |
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294 | * Configure stack for the AP. |
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295 | * The AP is expected to use the stack saved |
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296 | * in the ctx global variable. |
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297 | */ |
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298 | set ctx, %g1 |
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299 | add %g1, OFFSET_SP, %g1 |
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300 | ldx [%g1], %o6 |
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301 | |||
302 | call main_ap |
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303 | nop |
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304 | |||
305 | /* Not reached. */ |
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1905 | jermar | 306 | #endif |
1903 | jermar | 307 | |
308 | 0: |
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309 | ba 0b |
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310 | nop |
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1917 | jermar | 311 | |
312 | |||
313 | .section K_DATA_START, "aw", @progbits |
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314 | |||
315 | /* |
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316 | * Create small stack to be used by the bootstrap processor. |
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317 | * It is going to be used only for a very limited period of |
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318 | * time, but we switch to it anyway, just to be sure we are |
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319 | * properly initialized. |
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320 | * |
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321 | * What is important is that this piece of memory is covered |
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322 | * by the 4M DTLB locked entry and therefore there will be |
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323 | * no surprises like deadly combinations of spill trap and |
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324 | * and TLB miss on the stack address. |
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325 | */ |
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326 | |||
327 | #define INITIAL_STACK_SIZE 1024 |
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328 | |||
329 | .align STACK_ALIGNMENT |
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1978 | jermar | 330 | .space INITIAL_STACK_SIZE |
1917 | jermar | 331 | .align STACK_ALIGNMENT |
332 | temporary_boot_stack: |
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1978 | jermar | 333 | .space STACK_WINDOW_SAVE_AREA_SIZE |
334 | |||
335 | |||
336 | .data |
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337 | |||
338 | .align 8 |
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339 | .global physmem_base ! copy of the physical memory base address |
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340 | physmem_base: |
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341 | .quad 0 |
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342 | |||
343 | .global physmem_base_40_13 |
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344 | physmem_base_40_13: ! physmem_base & mask_40_13 |
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345 | .quad 0 |
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346 | |||
347 | .global mask_40_13 |
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348 | mask_40_13: ! constant with bits 40:13 set |
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349 | .quad (((1 << 41) - 1) & ~((1 << 13) - 1)) |
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350 | |||
351 | /* |
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352 | * This variable is used by the fast_data_MMU_miss trap handler. |
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353 | * It is initialized to reflect the starting address of physical |
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354 | * memory. |
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355 | */ |
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356 | .global kernel_8k_tlb_data_template |
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357 | kernel_8k_tlb_data_template: |
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358 | .quad ((1 << TTE_V_SHIFT) | TTE_CV | TTE_CP | TTE_P | TTE_W) |
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359 |