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418 | jermar | 1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | #ifndef __sparc64_TLB_H__ |
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30 | #define __sparc64_TLB_H__ |
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31 | |||
530 | jermar | 32 | #include <arch/mm/tte.h> |
617 | jermar | 33 | #include <arch/mm/page.h> |
569 | jermar | 34 | #include <arch/asm.h> |
613 | jermar | 35 | #include <arch/barrier.h> |
569 | jermar | 36 | #include <arch/types.h> |
37 | #include <typedefs.h> |
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530 | jermar | 38 | |
569 | jermar | 39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
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41 | |||
531 | jermar | 42 | /** I-MMU ASIs. */ |
43 | #define ASI_IMMU 0x50 |
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44 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
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45 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
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46 | #define ASI_ITLB_DATA_IN_REG 0x54 |
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47 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
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48 | #define ASI_ITLB_TAG_READ_REG 0x56 |
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49 | #define ASI_IMMU_DEMAP 0x57 |
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50 | |||
51 | /** Virtual Addresses within ASI_IMMU. */ |
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52 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
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53 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
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54 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
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55 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
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56 | |||
57 | /** D-MMU ASIs. */ |
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58 | #define ASI_DMMU 0x58 |
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59 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
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60 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
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61 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
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62 | #define ASI_DTLB_DATA_IN_REG 0x5c |
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63 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
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64 | #define ASI_DTLB_TAG_READ_REG 0x5e |
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65 | #define ASI_DMMU_DEMAP 0x5f |
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66 | |||
67 | /** Virtual Addresses within ASI_DMMU. */ |
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68 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
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69 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
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70 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
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71 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
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72 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
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73 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
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74 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
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75 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
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76 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
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77 | |||
530 | jermar | 78 | /** I-/D-TLB Data In/Access Register type. */ |
79 | typedef tte_data_t tlb_data_t; |
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80 | |||
569 | jermar | 81 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
82 | union tlb_data_access_addr { |
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83 | __u64 value; |
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84 | struct { |
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85 | __u64 : 55; |
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86 | unsigned tlb_entry : 6; |
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87 | unsigned : 3; |
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88 | } __attribute__ ((packed)); |
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89 | }; |
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90 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
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91 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
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418 | jermar | 92 | |
569 | jermar | 93 | /** I-/D-TLB Tag Read Register. */ |
94 | union tlb_tag_read_reg { |
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95 | __u64 value; |
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96 | struct { |
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617 | jermar | 97 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
569 | jermar | 98 | unsigned context : 13; /**< Context identifier. */ |
99 | } __attribute__ ((packed)); |
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100 | }; |
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101 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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613 | jermar | 102 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
569 | jermar | 103 | |
617 | jermar | 104 | /** TLB Demap Operation types. */ |
105 | #define TLB_DEMAP_PAGE 0 |
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106 | #define TLB_DEMAP_CONTEXT 1 |
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107 | |||
108 | /** TLB Demap Operation Context register encodings. */ |
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109 | #define TLB_DEMAP_PRIMARY 0 |
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110 | #define TLB_DEMAP_SECONDARY 1 |
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111 | #define TLB_DEMAP_NUCLEUS 2 |
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112 | |||
113 | /** TLB Demap Operation Address. */ |
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114 | union tlb_demap_addr { |
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115 | __u64 value; |
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116 | struct { |
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117 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
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118 | unsigned : 6; /**< Ignored. */ |
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119 | unsigned type : 1; /**< The type of demap operation. */ |
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120 | unsigned context : 2; /**< Context register selection. */ |
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121 | unsigned : 4; /**< Zero. */ |
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122 | } __attribute__ ((packed)); |
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123 | }; |
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124 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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125 | |||
569 | jermar | 126 | /** Read IMMU TLB Data Access Register. |
127 | * |
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128 | * @param entry TLB Entry index. |
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129 | * |
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130 | * @return Current value of specified IMMU TLB Data Access Register. |
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131 | */ |
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132 | static inline __u64 itlb_data_access_read(index_t entry) |
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133 | { |
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134 | tlb_data_access_addr_t reg; |
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135 | |||
136 | reg.value = 0; |
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137 | reg.tlb_entry = entry; |
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138 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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139 | } |
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140 | |||
617 | jermar | 141 | /** Write IMMU TLB Data Access Register. |
142 | * |
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143 | * @param entry TLB Entry index. |
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144 | * @param value Value to be written. |
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145 | */ |
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146 | static inline __u64 itlb_data_access_write(index_t entry, __u64 value) |
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147 | { |
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148 | tlb_data_access_addr_t reg; |
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149 | |||
150 | reg.value = 0; |
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151 | reg.tlb_entry = entry; |
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152 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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153 | flush(); |
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154 | } |
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155 | |||
569 | jermar | 156 | /** Read DMMU TLB Data Access Register. |
157 | * |
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158 | * @param entry TLB Entry index. |
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159 | * |
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160 | * @return Current value of specified DMMU TLB Data Access Register. |
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161 | */ |
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162 | static inline __u64 dtlb_data_access_read(index_t entry) |
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163 | { |
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164 | tlb_data_access_addr_t reg; |
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165 | |||
166 | reg.value = 0; |
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167 | reg.tlb_entry = entry; |
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168 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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169 | } |
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170 | |||
617 | jermar | 171 | /** Write DMMU TLB Data Access Register. |
172 | * |
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173 | * @param entry TLB Entry index. |
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174 | * @param value Value to be written. |
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175 | */ |
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176 | static inline __u64 dtlb_data_access_write(index_t entry, __u64 value) |
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177 | { |
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178 | tlb_data_access_addr_t reg; |
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179 | |||
180 | reg.value = 0; |
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181 | reg.tlb_entry = entry; |
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182 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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183 | flush(); |
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184 | } |
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185 | |||
569 | jermar | 186 | /** Read IMMU TLB Tag Read Register. |
187 | * |
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188 | * @param entry TLB Entry index. |
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189 | * |
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190 | * @return Current value of specified IMMU TLB Tag Read Register. |
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191 | */ |
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613 | jermar | 192 | static inline __u64 itlb_tag_read_read(index_t entry) |
569 | jermar | 193 | { |
194 | tlb_tag_read_addr_t tag; |
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195 | |||
196 | tag.value = 0; |
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197 | tag.tlb_entry = entry; |
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198 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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199 | } |
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200 | |||
201 | /** Read DMMU TLB Tag Read Register. |
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202 | * |
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203 | * @param entry TLB Entry index. |
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204 | * |
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205 | * @return Current value of specified DMMU TLB Tag Read Register. |
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206 | */ |
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613 | jermar | 207 | static inline __u64 dtlb_tag_read_read(index_t entry) |
569 | jermar | 208 | { |
209 | tlb_tag_read_addr_t tag; |
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210 | |||
211 | tag.value = 0; |
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212 | tag.tlb_entry = entry; |
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213 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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214 | } |
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215 | |||
613 | jermar | 216 | /** Write IMMU TLB Tag Access Register. |
217 | * |
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218 | * @param v Value to be written. |
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219 | */ |
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220 | static inline void itlb_tag_access_write(__u64 v) |
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221 | { |
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222 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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223 | flush(); |
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224 | } |
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225 | |||
226 | /** Write DMMU TLB Tag Access Register. |
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227 | * |
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228 | * @param v Value to be written. |
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229 | */ |
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230 | static inline void dtlb_tag_access_write(__u64 v) |
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231 | { |
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232 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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233 | flush(); |
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234 | } |
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235 | |||
236 | /** Write IMMU TLB Data in Register. |
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237 | * |
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238 | * @param v Value to be written. |
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239 | */ |
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240 | static inline void itlb_data_in_write(__u64 v) |
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241 | { |
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242 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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243 | flush(); |
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244 | } |
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245 | |||
246 | /** Write DMMU TLB Data in Register. |
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247 | * |
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248 | * @param v Value to be written. |
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249 | */ |
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250 | static inline void dtlb_data_in_write(__u64 v) |
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251 | { |
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252 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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253 | flush(); |
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254 | } |
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255 | |||
617 | jermar | 256 | /** Perform IMMU TLB Demap Operation. |
257 | * |
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258 | * @param type Selects between context and page demap. |
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259 | * @param context_encoding Specifies which Context register has Context ID for demap. |
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260 | * @param page Address which is on the page to be demapped. |
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261 | */ |
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262 | static inline void itlb_demap(int type, int context_encoding, __address page) |
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263 | { |
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264 | tlb_demap_addr_t da; |
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265 | page_address_t pg; |
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266 | |||
267 | da.value = 0; |
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268 | pg.address = page; |
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269 | |||
270 | da.type = type; |
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271 | da.context = context_encoding; |
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272 | da.vpn = pg.vpn; |
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273 | |||
274 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
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275 | flush(); |
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276 | } |
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277 | |||
278 | /** Perform DMMU TLB Demap Operation. |
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279 | * |
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280 | * @param type Selects between context and page demap. |
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281 | * @param context_encoding Specifies which Context register has Context ID for demap. |
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282 | * @param page Address which is on the page to be demapped. |
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283 | */ |
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284 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
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285 | { |
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286 | tlb_demap_addr_t da; |
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287 | page_address_t pg; |
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288 | |||
289 | da.value = 0; |
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290 | pg.address = page; |
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291 | |||
292 | da.type = type; |
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293 | da.context = context_encoding; |
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294 | da.vpn = pg.vpn; |
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295 | |||
296 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
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297 | flush(); |
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298 | } |
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299 | |||
418 | jermar | 300 | #endif |