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#
2071 jermar 2 
# Copyright (c) 2005 Martin Decky
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#include <arch/asm/regname.h>
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.text
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.global userspace_asm
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.global iret
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.global iret_syscall
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.global memsetb
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.global memcpy
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.global memcpy_from_uspace
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.global memcpy_to_uspace
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.global memcpy_from_uspace_failover_address
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.global memcpy_to_uspace_failover_address
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userspace_asm:
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	# r3 = uspace_uarg
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	# r4 = stack
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	# r5 = entry
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	# disable interrupts
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	mfmsr r31
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	rlwinm r31, r31, 0, 17, 15
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	mtmsr r31
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	# set entry point
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	mtsrr0 r5
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	# set problem state, enable interrupts
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	ori r31, r31, msr_pr
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	ori r31, r31, msr_ee
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	mtsrr1 r31
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	# set stack
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	mr sp, r4
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	# jump to userspace
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	rfi
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iret:
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	# disable interrupts
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	mfmsr r31
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	rlwinm r31, r31, 0, 17, 15
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	mtmsr r31
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	lwz r0, 8(sp)
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	lwz r2, 12(sp)
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	lwz r3, 16(sp)
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	lwz r4, 20(sp)
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	lwz r5, 24(sp)
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	lwz r6, 28(sp)
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	lwz r7, 32(sp)
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	lwz r8, 36(sp)
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	lwz r9, 40(sp)
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	lwz r10, 44(sp)
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	lwz r11, 48(sp)
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	lwz r13, 52(sp)
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	lwz r14, 56(sp)
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	lwz r15, 60(sp)
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	lwz r16, 64(sp)
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	lwz r17, 68(sp)
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	lwz r18, 72(sp)
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	lwz r19, 76(sp)
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	lwz r20, 80(sp)
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	lwz r21, 84(sp)
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	lwz r22, 88(sp)
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	lwz r23, 92(sp)
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	lwz r24, 96(sp)
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	lwz r25, 100(sp)
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	lwz r26, 104(sp)
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	lwz r27, 108(sp)
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	lwz r28, 112(sp)
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	lwz r29, 116(sp)
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	lwz r30, 120(sp)
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	lwz r31, 124(sp)
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	lwz r12, 128(sp)
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	mtcr r12
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	lwz r12, 132(sp)
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	mtsrr0 r12
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	lwz r12, 136(sp)
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	mtsrr1 r12
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1355 decky 121 
	lwz r12, 140(sp)
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	mtlr r12
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1355 decky 124 
	lwz r12, 144(sp)
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	mtctr r12
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1355 decky 127 
	lwz r12, 148(sp)
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	mtxer r12
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	lwz r12, 152(sp)
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	lwz sp, 156(sp)
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	rfi
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iret_syscall:
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	# reset decrementer
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	li r31, 1000
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	mtdec r31
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	# disable interrupts
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	mfmsr r31
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	rlwinm r31, r31, 0, 17, 15
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	mtmsr r31
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	lwz r0, 8(sp)
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	lwz r2, 12(sp)
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	lwz r4, 20(sp)
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	lwz r5, 24(sp)
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	lwz r6, 28(sp)
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	lwz r7, 32(sp)
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	lwz r8, 36(sp)
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	lwz r9, 40(sp)
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	lwz r10, 44(sp)
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	lwz r11, 48(sp)
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	lwz r13, 52(sp)
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	lwz r14, 56(sp)
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	lwz r15, 60(sp)
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	lwz r16, 64(sp)
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	lwz r17, 68(sp)
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	lwz r18, 72(sp)
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	lwz r19, 76(sp)
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	lwz r20, 80(sp)
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	lwz r21, 84(sp)
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	lwz r22, 88(sp)
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	lwz r23, 92(sp)
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	lwz r24, 96(sp)
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	lwz r25, 100(sp)
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	lwz r26, 104(sp)
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	lwz r27, 108(sp)
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	lwz r28, 112(sp)
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	lwz r29, 116(sp)
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	lwz r30, 120(sp)
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	lwz r31, 124(sp)
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	lwz r12, 128(sp)
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	mtcr r12
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	lwz r12, 132(sp)
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	mtsrr0 r12
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	lwz r12, 136(sp)
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	mtsrr1 r12
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	lwz r12, 140(sp)
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	mtlr r12
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	lwz r12, 144(sp)
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	mtctr r12
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	lwz r12, 148(sp)
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	mtxer r12
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	lwz r12, 152(sp)
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	lwz sp, 156(sp)
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	rfi
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memsetb:
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	b _memsetb
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memcpy:
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memcpy_from_uspace:
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memcpy_to_uspace:
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	srwi. r7, r5, 3
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	addi r6, r3, -4
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	addi r4, r4, -4
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	beq	2f
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	andi. r0, r6, 3
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	mtctr r7
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	bne 5f
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	1:
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	lwz r7, 4(r4)
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	lwzu r8, 8(r4)
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	stw r7, 4(r6)
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	stwu r8, 8(r6)
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	bdnz 1b
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	andi. r5, r5, 7
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	2:
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	cmplwi 0, r5, 4
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	blt 3f
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	lwzu r0, 4(r4)
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	addi r5, r5, -4
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	stwu r0, 4(r6)
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	3:
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	cmpwi 0, r5, 0
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	beqlr
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	mtctr r5
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	addi r4, r4, 3
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	addi r6, r6, 3
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	4:
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	lbzu r0, 1(r4)
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	stbu r0, 1(r6)
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	bdnz 4b
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	blr
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	5:
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	subfic r0, r0, 4
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	mtctr r0
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	6:
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	lbz r7, 4(r4)
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	addi r4, r4, 1
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	stb r7, 4(r6)
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	addi r6, r6, 1
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	bdnz 6b
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	subf r5, r0, r5
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	rlwinm. r7, r5, 32-3, 3, 31
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	beq 2b
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	mtctr r7
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	b 1b
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memcpy_from_uspace_failover_address:
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memcpy_to_uspace_failover_address:
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	# return zero, failure
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	xor r3, r3, r3
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	blr