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2726 vana 1
/*
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 * Copyright (c) 1999, 2000
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 * Intel Corporation.
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 *
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 *
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 * 3. All advertising materials mentioning features or use of this software
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 *    must display the following acknowledgement:
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 *
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 *    This product includes software developed by Intel Corporation and
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 *    its contributors.
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 *
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 * 4. Neither the name of Intel Corporation or its contributors may be
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 *    used to endorse or promote products derived from this software
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 *    without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS''
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 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED.  IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE
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 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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 * THE POSSIBILITY OF SUCH DAMAGE.
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 *
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 */
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#ifndef _EFICONTEXT_H_
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#define _EFICONTEXT_H_
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//
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//  IA-64 processor exception types
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//
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#define    EXCPT_ALT_DTLB            4
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#define    EXCPT_DNESTED_TLB         5
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#define    EXCPT_BREAKPOINT         11
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#define    EXCPT_EXTERNAL_INTERRUPT 12
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#define    EXCPT_GEN_EXCEPT         24
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#define    EXCPT_NAT_CONSUMPTION    26
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#define    EXCPT_DEBUG_EXCEPT       29
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#define    EXCPT_UNALIGNED_ACCESS   30
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#define    EXCPT_FP_FAULT           32
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#define    EXCPT_FP_TRAP            33
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#define    EXCPT_TAKEN_BRANCH       35
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#define    EXCPT_SINGLE_STEP        36
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//
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//  IA-64 processor context definition - must be 512 byte aligned!!!
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//
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typedef
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struct {
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    UINT64 reserved;    // necessary to preserve alignment for the correct bits in UNAT and to insure F2 is 16 byte aligned...
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    UINT64 r1;
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    UINT64 r2;
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    UINT64 r3;
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    UINT64 r4;
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    UINT64 r5;
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    UINT64 r6;
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    UINT64 r7;
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    UINT64 r8;
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    UINT64 r9;
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    UINT64 r10;
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    UINT64 r11;
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    UINT64 r12;
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    UINT64 r13;
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    UINT64 r14;
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    UINT64 r15;
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    UINT64 r16;
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    UINT64 r17;
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    UINT64 r18;
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    UINT64 r19;
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    UINT64 r20;
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    UINT64 r21;
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    UINT64 r22;
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    UINT64 r23;
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    UINT64 r24;
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    UINT64 r25;
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    UINT64 r26;
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    UINT64 r27;
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    UINT64 r28;
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    UINT64 r29;
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    UINT64 r30;
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    UINT64 r31;
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    UINT64 f2[2];
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    UINT64 f3[2];
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    UINT64 f4[2];
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    UINT64 f5[2];
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    UINT64 f6[2];
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    UINT64 f7[2];
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    UINT64 f8[2];
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    UINT64 f9[2];
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    UINT64 f10[2];
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    UINT64 f11[2];
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    UINT64 f12[2];
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    UINT64 f13[2];
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    UINT64 f14[2];
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    UINT64 f15[2];
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    UINT64 f16[2];
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    UINT64 f17[2];
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    UINT64 f18[2];
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    UINT64 f19[2];
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    UINT64 f20[2];
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    UINT64 f21[2];
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    UINT64 f22[2];
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    UINT64 f23[2];
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    UINT64 f24[2];
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    UINT64 f25[2];
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    UINT64 f26[2];
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    UINT64 f27[2];
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    UINT64 f28[2];
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    UINT64 f29[2];
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    UINT64 f30[2];
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    UINT64 f31[2];
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    UINT64 pr;
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    UINT64 b0;
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    UINT64 b1;
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    UINT64 b2;
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    UINT64 b3;
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    UINT64 b4;
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    UINT64 b5;
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    UINT64 b6;
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    UINT64 b7;
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    // application registers
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    UINT64 ar_rsc;
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    UINT64 ar_bsp;
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    UINT64 ar_bspstore;
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    UINT64 ar_rnat;
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    UINT64 ar_fcr;
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    UINT64 ar_eflag;
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    UINT64 ar_csd;
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    UINT64 ar_ssd;
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    UINT64 ar_cflg;
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    UINT64 ar_fsr;
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    UINT64 ar_fir;
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    UINT64 ar_fdr;
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    UINT64 ar_ccv;
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    UINT64 ar_unat;
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    UINT64 ar_fpsr;
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    UINT64 ar_pfs;
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    UINT64 ar_lc;
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    UINT64 ar_ec;
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    // control registers
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    UINT64 cr_dcr;
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    UINT64 cr_itm;
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    UINT64 cr_iva;
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    UINT64 cr_pta;
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    UINT64 cr_ipsr;
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    UINT64 cr_isr;
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    UINT64 cr_iip;
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    UINT64 cr_ifa;
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    UINT64 cr_itir;
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    UINT64 cr_iipa;
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    UINT64 cr_ifs;
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    UINT64 cr_iim;
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    UINT64 cr_iha;
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    // debug registers
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    UINT64 dbr0;
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    UINT64 dbr1;
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    UINT64 dbr2;
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    UINT64 dbr3;
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    UINT64 dbr4;
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    UINT64 dbr5;
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    UINT64 dbr6;
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    UINT64 dbr7;
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    UINT64 ibr0;
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    UINT64 ibr1;
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    UINT64 ibr2;
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    UINT64 ibr3;
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    UINT64 ibr4;
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    UINT64 ibr5;
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    UINT64 ibr6;
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    UINT64 ibr7;
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    // virtual registers
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    UINT64 int_nat; // nat bits for R1-R31
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} SYSTEM_CONTEXT;
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#endif /* _EFI_CONTEXT_H_ */