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756 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2006 Jakub Jermar |
756 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1860 | jermar | 29 | /** @addtogroup sparc64mm |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
756 | jermar | 35 | #include <arch/mm/as.h> |
1860 | jermar | 36 | #include <arch/mm/tlb.h> |
2089 | decky | 37 | #include <genarch/mm/page_ht.h> |
830 | jermar | 38 | #include <genarch/mm/asid_fifo.h> |
1890 | jermar | 39 | #include <debug.h> |
1903 | jermar | 40 | #include <config.h> |
756 | jermar | 41 | |
1890 | jermar | 42 | #ifdef CONFIG_TSB |
43 | #include <arch/mm/tsb.h> |
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1891 | jermar | 44 | #include <arch/memstr.h> |
45 | #include <arch/asm.h> |
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46 | #include <mm/frame.h> |
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47 | #include <bitops.h> |
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48 | #include <macros.h> |
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2009 | jermar | 49 | #endif /* CONFIG_TSB */ |
1890 | jermar | 50 | |
756 | jermar | 51 | /** Architecture dependent address space init. */ |
52 | void as_arch_init(void) |
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53 | { |
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1903 | jermar | 54 | if (config.cpu_active == 1) { |
55 | as_operations = &as_ht_operations; |
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56 | asid_fifo_init(); |
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57 | } |
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756 | jermar | 58 | } |
1702 | cejka | 59 | |
1891 | jermar | 60 | int as_constructor_arch(as_t *as, int flags) |
61 | { |
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62 | #ifdef CONFIG_TSB |
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2144 | jermar | 63 | /* |
64 | * The order must be calculated with respect to the emulated |
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65 | * 16K page size. |
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66 | */ |
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2048 | jermar | 67 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
2144 | jermar | 68 | sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
2272 | jermar | 69 | |
1987 | jermar | 70 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
1891 | jermar | 71 | |
72 | if (!tsb) |
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73 | return -1; |
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74 | |||
75 | as->arch.itsb = (tsb_entry_t *) tsb; |
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2048 | jermar | 76 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
2144 | jermar | 77 | sizeof(tsb_entry_t)); |
2272 | jermar | 78 | |
2141 | jermar | 79 | memsetb((uintptr_t) as->arch.itsb, |
80 | (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); |
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1891 | jermar | 81 | #endif |
82 | return 0; |
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83 | } |
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84 | |||
85 | int as_destructor_arch(as_t *as) |
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86 | { |
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87 | #ifdef CONFIG_TSB |
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2144 | jermar | 88 | /* |
89 | * The count must be calculated with respect to the emualted 16K page |
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90 | * size. |
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91 | */ |
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2048 | jermar | 92 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
2144 | jermar | 93 | sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
1987 | jermar | 94 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
1891 | jermar | 95 | return cnt; |
96 | #else |
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97 | return 0; |
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98 | #endif |
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99 | } |
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100 | |||
101 | int as_create_arch(as_t *as, int flags) |
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102 | { |
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103 | #ifdef CONFIG_TSB |
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104 | tsb_invalidate(as, 0, (count_t) -1); |
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105 | #endif |
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106 | return 0; |
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107 | } |
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108 | |||
2048 | jermar | 109 | /** Perform sparc64-specific tasks when an address space becomes active on the |
110 | * processor. |
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1890 | jermar | 111 | * |
112 | * Install ASID and map TSBs. |
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113 | * |
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114 | * @param as Address space. |
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115 | */ |
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1860 | jermar | 116 | void as_install_arch(as_t *as) |
117 | { |
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118 | tlb_context_reg_t ctx; |
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119 | |||
120 | /* |
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2170 | jermar | 121 | * Note that we don't and may not lock the address space. That's ok |
122 | * since we only read members that are currently read-only. |
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123 | * |
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124 | * Moreover, the as->asid is protected by asidlock, which is being held. |
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1890 | jermar | 125 | */ |
126 | |||
127 | /* |
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2170 | jermar | 128 | * Write ASID to secondary context register. The primary context |
129 | * register has to be set from TL>0 so it will be filled from the |
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130 | * secondary context register from the TL=1 code just before switch to |
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131 | * userspace. |
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1860 | jermar | 132 | */ |
133 | ctx.v = 0; |
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134 | ctx.context = as->asid; |
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135 | mmu_secondary_context_write(ctx.v); |
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1890 | jermar | 136 | |
137 | #ifdef CONFIG_TSB |
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1891 | jermar | 138 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
1890 | jermar | 139 | |
1891 | jermar | 140 | ASSERT(as->arch.itsb && as->arch.dtsb); |
1890 | jermar | 141 | |
1891 | jermar | 142 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
1890 | jermar | 143 | |
2141 | jermar | 144 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
1890 | jermar | 145 | /* |
1891 | jermar | 146 | * TSBs were allocated from memory not covered |
147 | * by the locked 4M kernel DTLB entry. We need |
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148 | * to map both TSBs explicitly. |
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1890 | jermar | 149 | */ |
1891 | jermar | 150 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
151 | dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); |
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152 | } |
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1890 | jermar | 153 | |
1891 | jermar | 154 | /* |
155 | * Setup TSB Base registers. |
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156 | */ |
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157 | tsb_base_reg_t tsb_base; |
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158 | |||
159 | tsb_base.value = 0; |
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160 | tsb_base.size = TSB_SIZE; |
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161 | tsb_base.split = 0; |
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1890 | jermar | 162 | |
2141 | jermar | 163 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; |
1891 | jermar | 164 | itsb_base_write(tsb_base.value); |
2141 | jermar | 165 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
1891 | jermar | 166 | dtsb_base_write(tsb_base.value); |
1890 | jermar | 167 | #endif |
1860 | jermar | 168 | } |
169 | |||
2048 | jermar | 170 | /** Perform sparc64-specific tasks when an address space is removed from the |
171 | * processor. |
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1890 | jermar | 172 | * |
173 | * Demap TSBs. |
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174 | * |
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175 | * @param as Address space. |
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176 | */ |
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177 | void as_deinstall_arch(as_t *as) |
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178 | { |
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179 | |||
180 | /* |
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2170 | jermar | 181 | * Note that we don't and may not lock the address space. That's ok |
182 | * since we only read members that are currently read-only. |
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183 | * |
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184 | * Moreover, the as->asid is protected by asidlock, which is being held. |
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1890 | jermar | 185 | */ |
186 | |||
187 | #ifdef CONFIG_TSB |
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1891 | jermar | 188 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
1890 | jermar | 189 | |
1891 | jermar | 190 | ASSERT(as->arch.itsb && as->arch.dtsb); |
1890 | jermar | 191 | |
1891 | jermar | 192 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
1890 | jermar | 193 | |
2141 | jermar | 194 | if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
1891 | jermar | 195 | /* |
196 | * TSBs were allocated from memory not covered |
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197 | * by the locked 4M kernel DTLB entry. We need |
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198 | * to demap the entry installed by as_install_arch(). |
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199 | */ |
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200 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
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1890 | jermar | 201 | } |
202 | #endif |
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203 | } |
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204 | |||
1860 | jermar | 205 | /** @} |
1702 | cejka | 206 | */ |