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418 | jermar | 1 | /* |
2071 | jermar | 2 | * Copyright (c) 2005 Jakub Jermar |
418 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
1822 | jermar | 29 | /** @addtogroup sparc64mm |
1702 | cejka | 30 | * @{ |
31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
1860 | jermar | 35 | #ifndef KERN_sparc64_TLB_H_ |
36 | #define KERN_sparc64_TLB_H_ |
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418 | jermar | 37 | |
569 | jermar | 38 | #define ITLB_ENTRY_COUNT 64 |
39 | #define DTLB_ENTRY_COUNT 64 |
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40 | |||
1823 | jermar | 41 | #define MEM_CONTEXT_KERNEL 0 |
42 | #define MEM_CONTEXT_TEMP 1 |
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43 | |||
619 | jermar | 44 | /** Page sizes. */ |
45 | #define PAGESIZE_8K 0 |
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46 | #define PAGESIZE_64K 1 |
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47 | #define PAGESIZE_512K 2 |
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48 | #define PAGESIZE_4M 3 |
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531 | jermar | 49 | |
901 | jermar | 50 | /** Bit width of the TLB-locked portion of kernel address space. */ |
51 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
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52 | |||
1823 | jermar | 53 | /* TLB Demap Operation types. */ |
54 | #define TLB_DEMAP_PAGE 0 |
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55 | #define TLB_DEMAP_CONTEXT 1 |
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56 | |||
57 | #define TLB_DEMAP_TYPE_SHIFT 6 |
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58 | |||
59 | /* TLB Demap Operation Context register encodings. */ |
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60 | #define TLB_DEMAP_PRIMARY 0 |
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61 | #define TLB_DEMAP_SECONDARY 1 |
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62 | #define TLB_DEMAP_NUCLEUS 2 |
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63 | |||
64 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
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65 | |||
66 | /* TLB Tag Access shifts */ |
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67 | #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
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2054 | jermar | 68 | #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
1823 | jermar | 69 | #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
70 | |||
71 | #ifndef __ASM__ |
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72 | |||
73 | #include <arch/mm/tte.h> |
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74 | #include <arch/mm/mmu.h> |
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75 | #include <arch/mm/page.h> |
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76 | #include <arch/asm.h> |
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77 | #include <arch/barrier.h> |
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78 | #include <arch/types.h> |
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79 | |||
873 | jermar | 80 | union tlb_context_reg { |
1780 | jermar | 81 | uint64_t v; |
873 | jermar | 82 | struct { |
83 | unsigned long : 51; |
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84 | unsigned context : 13; /**< Context/ASID. */ |
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85 | } __attribute__ ((packed)); |
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86 | }; |
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87 | typedef union tlb_context_reg tlb_context_reg_t; |
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88 | |||
530 | jermar | 89 | /** I-/D-TLB Data In/Access Register type. */ |
90 | typedef tte_data_t tlb_data_t; |
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91 | |||
569 | jermar | 92 | /** I-/D-TLB Data Access Address in Alternate Space. */ |
93 | union tlb_data_access_addr { |
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1780 | jermar | 94 | uint64_t value; |
569 | jermar | 95 | struct { |
1780 | jermar | 96 | uint64_t : 55; |
569 | jermar | 97 | unsigned tlb_entry : 6; |
98 | unsigned : 3; |
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99 | } __attribute__ ((packed)); |
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100 | }; |
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101 | typedef union tlb_data_access_addr tlb_data_access_addr_t; |
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102 | typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
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418 | jermar | 103 | |
569 | jermar | 104 | /** I-/D-TLB Tag Read Register. */ |
105 | union tlb_tag_read_reg { |
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1780 | jermar | 106 | uint64_t value; |
569 | jermar | 107 | struct { |
2054 | jermar | 108 | uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
109 | unsigned context : 13; /**< Context identifier. */ |
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569 | jermar | 110 | } __attribute__ ((packed)); |
111 | }; |
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112 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
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613 | jermar | 113 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
569 | jermar | 114 | |
617 | jermar | 115 | |
116 | /** TLB Demap Operation Address. */ |
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117 | union tlb_demap_addr { |
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1780 | jermar | 118 | uint64_t value; |
617 | jermar | 119 | struct { |
1851 | jermar | 120 | uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
617 | jermar | 121 | unsigned : 6; /**< Ignored. */ |
122 | unsigned type : 1; /**< The type of demap operation. */ |
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123 | unsigned context : 2; /**< Context register selection. */ |
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124 | unsigned : 4; /**< Zero. */ |
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125 | } __attribute__ ((packed)); |
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126 | }; |
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127 | typedef union tlb_demap_addr tlb_demap_addr_t; |
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128 | |||
873 | jermar | 129 | /** TLB Synchronous Fault Status Register. */ |
130 | union tlb_sfsr_reg { |
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1780 | jermar | 131 | uint64_t value; |
873 | jermar | 132 | struct { |
1851 | jermar | 133 | unsigned long : 40; /**< Implementation dependent. */ |
873 | jermar | 134 | unsigned asi : 8; /**< ASI. */ |
1851 | jermar | 135 | unsigned : 2; |
877 | jermar | 136 | unsigned ft : 7; /**< Fault type. */ |
873 | jermar | 137 | unsigned e : 1; /**< Side-effect bit. */ |
138 | unsigned ct : 2; /**< Context Register selection. */ |
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139 | unsigned pr : 1; /**< Privilege bit. */ |
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140 | unsigned w : 1; /**< Write bit. */ |
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141 | unsigned ow : 1; /**< Overwrite bit. */ |
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877 | jermar | 142 | unsigned fv : 1; /**< Fault Valid bit. */ |
873 | jermar | 143 | } __attribute__ ((packed)); |
144 | }; |
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145 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
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146 | |||
147 | /** Read MMU Primary Context Register. |
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148 | * |
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149 | * @return Current value of Primary Context Register. |
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150 | */ |
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1780 | jermar | 151 | static inline uint64_t mmu_primary_context_read(void) |
873 | jermar | 152 | { |
153 | return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
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154 | } |
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155 | |||
156 | /** Write MMU Primary Context Register. |
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157 | * |
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158 | * @param v New value of Primary Context Register. |
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159 | */ |
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1780 | jermar | 160 | static inline void mmu_primary_context_write(uint64_t v) |
873 | jermar | 161 | { |
162 | asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
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163 | flush(); |
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164 | } |
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165 | |||
166 | /** Read MMU Secondary Context Register. |
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167 | * |
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168 | * @return Current value of Secondary Context Register. |
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169 | */ |
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1780 | jermar | 170 | static inline uint64_t mmu_secondary_context_read(void) |
873 | jermar | 171 | { |
172 | return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
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173 | } |
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174 | |||
175 | /** Write MMU Primary Context Register. |
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176 | * |
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177 | * @param v New value of Primary Context Register. |
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178 | */ |
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1780 | jermar | 179 | static inline void mmu_secondary_context_write(uint64_t v) |
873 | jermar | 180 | { |
1864 | jermar | 181 | asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
873 | jermar | 182 | flush(); |
183 | } |
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184 | |||
569 | jermar | 185 | /** Read IMMU TLB Data Access Register. |
186 | * |
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187 | * @param entry TLB Entry index. |
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188 | * |
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189 | * @return Current value of specified IMMU TLB Data Access Register. |
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190 | */ |
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1780 | jermar | 191 | static inline uint64_t itlb_data_access_read(index_t entry) |
569 | jermar | 192 | { |
193 | tlb_data_access_addr_t reg; |
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194 | |||
195 | reg.value = 0; |
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196 | reg.tlb_entry = entry; |
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197 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
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198 | } |
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199 | |||
617 | jermar | 200 | /** Write IMMU TLB Data Access Register. |
201 | * |
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202 | * @param entry TLB Entry index. |
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203 | * @param value Value to be written. |
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204 | */ |
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1780 | jermar | 205 | static inline void itlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 206 | { |
207 | tlb_data_access_addr_t reg; |
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208 | |||
209 | reg.value = 0; |
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210 | reg.tlb_entry = entry; |
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211 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
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212 | flush(); |
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213 | } |
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214 | |||
569 | jermar | 215 | /** Read DMMU TLB Data Access Register. |
216 | * |
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217 | * @param entry TLB Entry index. |
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218 | * |
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219 | * @return Current value of specified DMMU TLB Data Access Register. |
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220 | */ |
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1780 | jermar | 221 | static inline uint64_t dtlb_data_access_read(index_t entry) |
569 | jermar | 222 | { |
223 | tlb_data_access_addr_t reg; |
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224 | |||
225 | reg.value = 0; |
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226 | reg.tlb_entry = entry; |
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227 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
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228 | } |
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229 | |||
617 | jermar | 230 | /** Write DMMU TLB Data Access Register. |
231 | * |
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232 | * @param entry TLB Entry index. |
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233 | * @param value Value to be written. |
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234 | */ |
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1780 | jermar | 235 | static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
617 | jermar | 236 | { |
237 | tlb_data_access_addr_t reg; |
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238 | |||
239 | reg.value = 0; |
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240 | reg.tlb_entry = entry; |
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241 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
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1822 | jermar | 242 | membar(); |
617 | jermar | 243 | } |
244 | |||
569 | jermar | 245 | /** Read IMMU TLB Tag Read Register. |
246 | * |
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247 | * @param entry TLB Entry index. |
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248 | * |
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249 | * @return Current value of specified IMMU TLB Tag Read Register. |
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250 | */ |
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1780 | jermar | 251 | static inline uint64_t itlb_tag_read_read(index_t entry) |
569 | jermar | 252 | { |
253 | tlb_tag_read_addr_t tag; |
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254 | |||
255 | tag.value = 0; |
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256 | tag.tlb_entry = entry; |
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257 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
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258 | } |
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259 | |||
260 | /** Read DMMU TLB Tag Read Register. |
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261 | * |
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262 | * @param entry TLB Entry index. |
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263 | * |
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264 | * @return Current value of specified DMMU TLB Tag Read Register. |
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265 | */ |
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1780 | jermar | 266 | static inline uint64_t dtlb_tag_read_read(index_t entry) |
569 | jermar | 267 | { |
268 | tlb_tag_read_addr_t tag; |
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269 | |||
270 | tag.value = 0; |
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271 | tag.tlb_entry = entry; |
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272 | return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
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273 | } |
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274 | |||
613 | jermar | 275 | /** Write IMMU TLB Tag Access Register. |
276 | * |
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277 | * @param v Value to be written. |
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278 | */ |
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1780 | jermar | 279 | static inline void itlb_tag_access_write(uint64_t v) |
613 | jermar | 280 | { |
281 | asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
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282 | flush(); |
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283 | } |
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284 | |||
877 | jermar | 285 | /** Read IMMU TLB Tag Access Register. |
286 | * |
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287 | * @return Current value of IMMU TLB Tag Access Register. |
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288 | */ |
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1780 | jermar | 289 | static inline uint64_t itlb_tag_access_read(void) |
877 | jermar | 290 | { |
291 | return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
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292 | } |
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293 | |||
613 | jermar | 294 | /** Write DMMU TLB Tag Access Register. |
295 | * |
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296 | * @param v Value to be written. |
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297 | */ |
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1780 | jermar | 298 | static inline void dtlb_tag_access_write(uint64_t v) |
613 | jermar | 299 | { |
300 | asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
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1822 | jermar | 301 | membar(); |
613 | jermar | 302 | } |
303 | |||
877 | jermar | 304 | /** Read DMMU TLB Tag Access Register. |
305 | * |
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306 | * @return Current value of DMMU TLB Tag Access Register. |
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307 | */ |
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1780 | jermar | 308 | static inline uint64_t dtlb_tag_access_read(void) |
877 | jermar | 309 | { |
310 | return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
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311 | } |
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312 | |||
313 | |||
613 | jermar | 314 | /** Write IMMU TLB Data in Register. |
315 | * |
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316 | * @param v Value to be written. |
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317 | */ |
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1780 | jermar | 318 | static inline void itlb_data_in_write(uint64_t v) |
613 | jermar | 319 | { |
320 | asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
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321 | flush(); |
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322 | } |
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323 | |||
324 | /** Write DMMU TLB Data in Register. |
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325 | * |
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326 | * @param v Value to be written. |
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327 | */ |
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1780 | jermar | 328 | static inline void dtlb_data_in_write(uint64_t v) |
613 | jermar | 329 | { |
330 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
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1822 | jermar | 331 | membar(); |
613 | jermar | 332 | } |
333 | |||
873 | jermar | 334 | /** Read ITLB Synchronous Fault Status Register. |
335 | * |
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336 | * @return Current content of I-SFSR register. |
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337 | */ |
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1780 | jermar | 338 | static inline uint64_t itlb_sfsr_read(void) |
873 | jermar | 339 | { |
340 | return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
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341 | } |
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342 | |||
343 | /** Write ITLB Synchronous Fault Status Register. |
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344 | * |
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345 | * @param v New value of I-SFSR register. |
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346 | */ |
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1780 | jermar | 347 | static inline void itlb_sfsr_write(uint64_t v) |
873 | jermar | 348 | { |
349 | asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
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350 | flush(); |
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351 | } |
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352 | |||
353 | /** Read DTLB Synchronous Fault Status Register. |
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354 | * |
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355 | * @return Current content of D-SFSR register. |
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356 | */ |
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1780 | jermar | 357 | static inline uint64_t dtlb_sfsr_read(void) |
873 | jermar | 358 | { |
359 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
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360 | } |
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361 | |||
362 | /** Write DTLB Synchronous Fault Status Register. |
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363 | * |
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364 | * @param v New value of D-SFSR register. |
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365 | */ |
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1780 | jermar | 366 | static inline void dtlb_sfsr_write(uint64_t v) |
873 | jermar | 367 | { |
368 | asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
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1822 | jermar | 369 | membar(); |
873 | jermar | 370 | } |
371 | |||
372 | /** Read DTLB Synchronous Fault Address Register. |
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373 | * |
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374 | * @return Current content of D-SFAR register. |
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375 | */ |
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1780 | jermar | 376 | static inline uint64_t dtlb_sfar_read(void) |
873 | jermar | 377 | { |
378 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
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379 | } |
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380 | |||
617 | jermar | 381 | /** Perform IMMU TLB Demap Operation. |
382 | * |
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383 | * @param type Selects between context and page demap. |
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2054 | jermar | 384 | * @param context_encoding Specifies which Context register has Context ID for |
385 | * demap. |
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617 | jermar | 386 | * @param page Address which is on the page to be demapped. |
387 | */ |
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1780 | jermar | 388 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 389 | { |
390 | tlb_demap_addr_t da; |
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391 | page_address_t pg; |
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392 | |||
393 | da.value = 0; |
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394 | pg.address = page; |
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395 | |||
396 | da.type = type; |
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397 | da.context = context_encoding; |
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398 | da.vpn = pg.vpn; |
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399 | |||
2054 | jermar | 400 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
401 | * address within the |
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402 | * ASI */ |
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617 | jermar | 403 | flush(); |
404 | } |
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405 | |||
406 | /** Perform DMMU TLB Demap Operation. |
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407 | * |
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408 | * @param type Selects between context and page demap. |
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2054 | jermar | 409 | * @param context_encoding Specifies which Context register has Context ID for |
410 | * demap. |
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617 | jermar | 411 | * @param page Address which is on the page to be demapped. |
412 | */ |
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1780 | jermar | 413 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
617 | jermar | 414 | { |
415 | tlb_demap_addr_t da; |
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416 | page_address_t pg; |
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417 | |||
418 | da.value = 0; |
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419 | pg.address = page; |
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420 | |||
421 | da.type = type; |
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422 | da.context = context_encoding; |
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423 | da.vpn = pg.vpn; |
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424 | |||
2054 | jermar | 425 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
426 | * address within the |
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427 | * ASI */ |
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1822 | jermar | 428 | membar(); |
617 | jermar | 429 | } |
430 | |||
2231 | jermar | 431 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
432 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
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433 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
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863 | jermar | 434 | |
1780 | jermar | 435 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
897 | jermar | 436 | |
1946 | jermar | 437 | extern void dump_sfsr_and_sfar(void); |
438 | |||
1823 | jermar | 439 | #endif /* !def __ASM__ */ |
440 | |||
418 | jermar | 441 | #endif |
1702 | cejka | 442 | |
1822 | jermar | 443 | /** @} |
1702 | cejka | 444 | */ |