Subversion Repositories HelenOS

Rev

Rev 2955 | Rev 4343 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed

Rev Author Line No. Line
153 jermar 1
/*
2071 jermar 2
 * Copyright (c) 2005 Jakub Jermar
153 jermar 3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 *
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
28
 
1888 jermar 29
/** @addtogroup ia32   
1702 cejka 30
 * @{
31
 */
32
/** @file
33
 */
34
 
1888 jermar 35
#ifndef KERN_ia32_BARRIER_H_
36
#define KERN_ia32_BARRIER_H_
153 jermar 37
 
38
/*
39
 * NOTE:
40
 * No barriers for critical section (i.e. spinlock) on IA-32 are needed:
41
 * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction
42
 * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers
43
 */
44
 
45
/*
46
 * Provisions are made to prevent compiler from reordering instructions itself.
47
 */
48
 
2082 decky 49
#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
50
#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
153 jermar 51
 
469 jermar 52
static inline void cpuid_serialization(void)
53
{
2955 svoboda 54
#ifndef __PIC__
2082 decky 55
    asm volatile (
469 jermar 56
        "xorl %%eax, %%eax\n"
57
        "cpuid\n"
58
        ::: "eax", "ebx", "ecx", "edx", "memory"
59
    );
2955 svoboda 60
#else
61
    /* Must not clobber PIC register ebx */
62
    asm volatile (
63
        "movl %%ebx, %%esi\n"
64
        "xorl %%eax, %%eax\n"
65
        "cpuid\n"
66
        "movl %%esi, %%ebx\n"
67
        ::: "eax", "ecx", "edx", "esi", "memory"
68
    );
69
#endif
469 jermar 70
}
71
 
468 decky 72
#ifdef CONFIG_FENCES_P4
2082 decky 73
#   define memory_barrier()     asm volatile ("mfence\n" ::: "memory")
74
#   define read_barrier()       asm volatile ("lfence\n" ::: "memory")
470 jermar 75
#   ifdef CONFIG_WEAK_MEMORY
2082 decky 76
#       define write_barrier()  asm volatile ("sfence\n" ::: "memory")
470 jermar 77
#   else
2082 decky 78
#       define write_barrier()  asm volatile( "" ::: "memory");
470 jermar 79
#   endif
468 decky 80
#elif CONFIG_FENCES_P3
469 jermar 81
#   define memory_barrier()     cpuid_serialization()
82
#   define read_barrier()       cpuid_serialization()
470 jermar 83
#   ifdef CONFIG_WEAK_MEMORY
2082 decky 84
#       define write_barrier()  asm volatile ("sfence\n" ::: "memory")
470 jermar 85
#   else
2082 decky 86
#       define write_barrier()  asm volatile( "" ::: "memory");
470 jermar 87
#   endif
469 jermar 88
#else
89
#   define memory_barrier()     cpuid_serialization()
90
#   define read_barrier()       cpuid_serialization()
470 jermar 91
#   ifdef CONFIG_WEAK_MEMORY
92
#       define write_barrier()  cpuid_serialization()
93
#   else
2082 decky 94
#       define write_barrier()  asm volatile( "" ::: "memory");
470 jermar 95
#   endif
153 jermar 96
#endif
423 decky 97
 
3153 svoboda 98
/*
99
 * On ia32, the hardware takes care about instruction and data cache coherence,
100
 * even on SMP systems.  We issue a write barrier to be sure that writes
101
 * queueing in the store buffer drain to the memory (even though it would be
102
 * sufficient for them to drain to the D-cache).
103
 */
104
#define smc_coherence(a)        write_barrier()
105
#define smc_coherence_block(a, l)   write_barrier()
106
 
423 decky 107
#endif
1702 cejka 108
 
1888 jermar 109
/** @}
1702 cejka 110
 */