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4221 trochtova 1
#include <unistd.h>
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#include <ddi.h>
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#include <libarch/ddi.h>
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#include <stdio.h>
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#include "internal.h"
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#include "header.h"
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/* physical addresses and offsets */
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#define U2P_BASE        0x1FE00000000
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#define PCI_CONF_OFFSET   0x001000000
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#define PCI_CONF_SIZE     0x001000000
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#define PCI_CONF_BASE  (U2P_BASE + PCI_CONF_OFFSET)
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/* virtual address of PCI configuration space */
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static void *conf_addr = 0;  
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/*
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 * virtual address of specified PCI configuration register:
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 * bus ... bus number (0 for top level PCI bus B, 1 for top level PCI bus A)
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 * dev ... device number (0 - 15)
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 * fn  ... function number (0 - 7)
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 * reg ... register number (register's position within PCI configuration header)
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 **/
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#define CONF_ADDR(bus, dev, fn, reg)   (conf_addr + ((bus << 16) | (dev << 11) | (fn << 8) | (reg << 2)))
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static void us2i_init(struct pci_access *a)
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{  
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}
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static void us2i_cleanup(struct pci_access *a UNUSED)
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{
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}
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static int us2i_detect(struct pci_access *a)
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{
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    unsigned int tmp;
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    /*
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     * Gain control over PCI configuration ports.
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     */
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    if (pio_enable((void *)PCI_CONF_BASE, PCI_CONF_SIZE, &conf_addr)) {
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        return 0;
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    }
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    printf("PCI: conf_addr = %lx", conf_addr);
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    printf("PCI: vendor id address = %lx", CONF_ADDR(0, 0, 0, PCI_VENDOR_ID));
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    asm volatile ("sethi 0x42224, %g0");
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    int vendor_id = pio_read_16(CONF_ADDR(0, 0, 0, PCI_VENDOR_ID));
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    vendor_id = vendor_id | pio_read_8(CONF_ADDR(0, 0, 0, PCI_VENDOR_ID + 1)) << 8;
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    int device_id = pio_read_8(CONF_ADDR(0, 0, 0, PCI_DEVICE_ID));
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    device_id = device_id | pio_read_8(CONF_ADDR(0, 0, 0, PCI_DEVICE_ID + 1)) << 8;
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    printf("PCI: vendor id = %x", vendor_id);
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    printf("PCI: device id = %x", device_id);
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    return vendor_id == 0x108E && device_id == 0x8000; // should be Psycho from Sun Microsystems
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}
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static int us2i_read(struct pci_dev *d, int pos, byte * buf, int len)
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{
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    if (pos >= 256)
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        return 0;      
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    switch (len) {
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    case 1:
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        buf[0] = pio_read_8(CONF_ADDR(d->bus, d->dev, d->func, pos));
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        break;
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    case 2:
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        us2i_read(d, pos + 1, buf, 1);   // unlike PCI, sparc uses big endian
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        us2i_read(d, pos, buf + 1, 1);
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        break;
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    case 4:
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        us2i_read(d, pos + 3, buf, 1);  // endians in an ugly way ... FIX ME 
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        us2i_read(d, pos + 2, buf + 1, 1);
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        us2i_read(d, pos + 1, buf + 2, 1);
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        us2i_read(d, pos, buf + 3, 1);     
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        break;
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    default:
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        return pci_generic_block_read(d, pos, buf, len);
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    }
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    return 1;
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}
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static int us2i_write(struct pci_dev *d, int pos, byte * buf, int len)
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{
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    if (pos >= 256)
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        return 0;
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    switch (len) {
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    case 1:
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        pio_write_8(CONF_ADDR(d->bus, d->dev, d->func, pos), buf[0]);
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        break;
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    case 2:
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        us2i_write(d, pos + 1, buf, 1);   // unlike PCI, sparc uses big endian
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        us2i_write(d, pos, buf + 1, 1);
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        break;
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    case 4:
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        us2i_write(d, pos + 3, buf, 1);  // endians in an ugly way ... FIX ME 
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        us2i_write(d, pos + 2, buf + 1, 1);
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        us2i_write(d, pos + 1, buf + 2, 1);
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        us2i_write(d, pos, buf + 3, 1);
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        break;
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    default:
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        return pci_generic_block_write(d, pos, buf, len);
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    }
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    return 1;
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}
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struct pci_methods pm_us2i = {
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    "Ultra Sparc IIi",
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    NULL,           /* config */
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    us2i_detect,
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    us2i_init,
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    us2i_cleanup,
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    pci_generic_scan,
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    pci_generic_fill_info,
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    us2i_read,
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    us2i_write,
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    NULL,           /* init_dev */
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    NULL            /* cleanup_dev */
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};