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| Rev | Author | Line No. | Line |
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| 4269 | trochtova | 1 | #include <unistd.h> |
| 2 | #include <ddi.h> |
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| 3 | #include <libarch/ddi.h> |
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| 4 | #include <stdio.h> |
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| 5 | |||
| 6 | #include "internal.h" |
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| 7 | |||
| 8 | /* physical addresses and offsets */ |
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| 9 | //#define U2P_BASE 0x1FE00000000 |
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| 10 | #define U2P_BASE 0x1c800000000 |
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| 11 | #define PCI_CONF_OFFSET 0x001000000 |
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| 12 | #define PCI_CONF_SIZE 0x001000000 |
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| 13 | #define PCI_CONF_BASE (U2P_BASE + PCI_CONF_OFFSET) |
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| 14 | |||
| 15 | /* virtual address of PCI configuration space */ |
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| 16 | static void *conf_addr = 0; |
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| 17 | |||
| 18 | /* |
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| 19 | * virtual address of specified PCI configuration register: |
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| 20 | * bus ... bus number (0 for top level PCI bus B, 1 for top level PCI bus A) |
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| 21 | * dev ... device number (0 - 15) |
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| 22 | * fn ... function number (0 - 7) |
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| 23 | * reg ... register number (register's position within PCI configuration header) |
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| 24 | **/ |
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| 25 | #define CONF_ADDR(bus, dev, fn, reg) ((void *)(conf_addr + ((bus << 16) | (dev << 11) | (fn << 8) | (reg << 0)))) |
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| 26 | |||
| 27 | |||
| 28 | |||
| 29 | static void us2i_init(struct pci_access *a) |
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| 30 | { |
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| 31 | } |
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| 32 | |||
| 33 | static void us2i_cleanup(struct pci_access *a UNUSED) |
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| 34 | { |
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| 35 | } |
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| 36 | |||
| 37 | static inline uint64_t pio_read_64(uint64_t *port) |
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| 38 | { |
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| 39 | uint64_t rv; |
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| 40 | |||
| 41 | rv = *port; |
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| 42 | memory_barrier(); |
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| 43 | |||
| 44 | return rv; |
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| 45 | } |
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| 46 | |||
| 47 | static int us2i_detect(struct pci_access *a) |
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| 48 | { |
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| 49 | /* |
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| 50 | * Gain control over PCI configuration ports. |
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| 51 | */ |
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| 52 | if (pio_enable((void *)PCI_CONF_BASE, PCI_CONF_SIZE, &conf_addr)) { |
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| 53 | return 0; |
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| 54 | } |
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| 55 | |||
| 56 | int vendor_id = le16_to_cpu(pio_read_16(CONF_ADDR(0, 0, 0, PCI_VENDOR_ID))); |
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| 57 | int device_id = le16_to_cpu(pio_read_16(CONF_ADDR(0, 0, 0, PCI_DEVICE_ID))); |
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| 58 | |||
| 59 | printf("PCI: vendor id = %x\n", vendor_id); |
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| 60 | printf("PCI: device id = %x\n", device_id); |
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| 61 | |||
| 62 | return vendor_id == 0x108E && device_id == 0x8000; // should be Psycho from Sun Microsystems |
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| 63 | } |
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| 64 | |||
| 65 | /** Compute new starting position of the operation if byte twisting is used. |
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| 66 | * |
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| 67 | * See chapter 10.2 of the UPA to PCI Interface User's Manual. |
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| 68 | * Note: byte twisting is used only for devices beyond the UPA |
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| 69 | * to PCI bridge, not for the device of the bridge itself. |
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| 70 | * Configuration registers of the bridge must be read in a different way. |
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| 71 | * |
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| 72 | * @param pos The original starting position of the read/write operation. |
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| 73 | * @param len The length of the read/write operation (<= 4). |
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| 74 | * @return New starting position of the operation. |
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| 75 | */ |
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| 76 | static int byte_twist(int pos, int len) |
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| 77 | { |
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| 78 | int end = (pos + len) % 4; |
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| 79 | if (end == 0) { |
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| 80 | end = 4; |
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| 81 | } |
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| 82 | int begin = 4 - end; |
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| 83 | pos = pos - pos % 4 + begin; |
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| 84 | return pos; |
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| 85 | } |
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| 86 | |||
| 87 | /* |
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| 88 | static int byte_twist(pos) |
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| 89 | { |
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| 90 | return pos - pos % 4 + (3 - pos % 4); |
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| 91 | }*/ |
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| 92 | |||
| 93 | static int us2i_read(struct pci_dev *d, int pos, byte * buf, int len) |
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| 94 | { |
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| 95 | /*void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos); |
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| 96 | |||
| 97 | if (pos >= 256) |
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| 98 | return 0; |
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| 99 | |||
| 100 | switch (len) { |
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| 101 | case 1: |
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| 102 | us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len); |
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| 103 | break; |
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| 104 | case 2: |
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| 105 | us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len); |
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| 106 | ((u16 *) buf)[0] = cpu_to_le16(*((u16 *) buf)); |
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| 107 | break; |
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| 108 | case 4: |
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| 109 | us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len); |
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| 110 | ((u32 *) buf)[0] = cpu_to_le32(*((u32 *) buf)); |
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| 111 | break; |
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| 112 | default: |
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| 113 | return pci_generic_block_read(d, pos, buf, len); |
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| 114 | } |
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| 115 | return 1; */ |
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| 116 | |||
| 117 | |||
| 118 | if (len <= 4) { |
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| 119 | int twist = d->dev != 0 || d->func != 0; |
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| 120 | if (twist) { |
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| 121 | pos = byte_twist(pos, len); |
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| 122 | } |
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| 123 | int i; |
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| 124 | for (i = 0; i < len; i++) { |
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| 125 | void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos + i); |
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| 126 | if (byte_twist) { |
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| 127 | buf[i] = pio_read_8(addr); |
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| 128 | } |
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| 129 | else { |
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| 130 | buf[len-i-1] = pio_read_8(addr); |
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| 131 | } |
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| 132 | } |
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| 133 | } else { |
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| 134 | return pci_generic_block_read(d, pos, buf, len); |
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| 135 | } |
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| 136 | return 1; |
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| 137 | |||
| 138 | /*void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos); |
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| 139 | |||
| 140 | if (pos >= 256) |
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| 141 | return 0; |
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| 142 | |||
| 143 | switch (len) { |
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| 144 | case 1: |
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| 145 | buf[0] = pio_read_8(addr); |
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| 146 | break; |
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| 147 | case 2: |
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| 148 | ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr)); |
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| 149 | break; |
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| 150 | case 4: |
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| 151 | ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr)); |
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| 152 | break; |
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| 153 | default: |
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| 154 | return pci_generic_block_read(d, pos, buf, len); |
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| 155 | } |
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| 156 | return 1; */ |
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| 157 | |||
| 158 | /* |
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| 159 | switch (len) { |
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| 160 | case 1: |
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| 161 | buf[0] = pio_read_8(CONF_ADDR(d->bus, d->dev, d->func, pos)); |
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| 162 | break; |
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| 163 | case 2: |
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| 164 | us2i_read(d, pos + 1, buf, 1); // unlike PCI, sparc uses big endian |
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| 165 | us2i_read(d, pos, buf + 1, 1); |
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| 166 | break; |
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| 167 | case 4: |
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| 168 | us2i_read(d, pos + 3, buf, 1); // endians in an ugly way ... FIX ME |
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| 169 | us2i_read(d, pos + 2, buf + 1, 1); |
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| 170 | us2i_read(d, pos + 1, buf + 2, 1); |
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| 171 | us2i_read(d, pos, buf + 3, 1); |
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| 172 | break; |
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| 173 | default: |
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| 174 | return pci_generic_block_read(d, pos, buf, len); |
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| 175 | } |
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| 176 | return 1; |
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| 177 | */ |
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| 178 | } |
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| 179 | |||
| 180 | static int us2i_write(struct pci_dev *d, int pos, byte * buf, int len) |
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| 181 | { |
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| 182 | void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos); |
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| 183 | |||
| 184 | if (pos >= 256) |
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| 185 | return 0; |
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| 186 | |||
| 187 | switch (len) { |
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| 188 | case 1: |
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| 189 | pio_write_8(CONF_ADDR(d->bus, d->dev, d->func, pos), buf[0]); |
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| 190 | break; |
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| 191 | case 2: |
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| 192 | pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0])); |
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| 193 | break; |
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| 194 | case 4: |
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| 195 | pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0])); |
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| 196 | break; |
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| 197 | default: |
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| 198 | return pci_generic_block_write(d, pos, buf, len); |
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| 199 | } |
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| 200 | return 1; |
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| 201 | } |
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| 202 | |||
| 203 | |||
| 204 | struct pci_methods pm_us2i = { |
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| 205 | "Ultra Sparc IIi", |
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| 206 | NULL, /* config */ |
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| 207 | us2i_detect, |
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| 208 | us2i_init, |
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| 209 | us2i_cleanup, |
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| 210 | pci_generic_scan, |
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| 211 | pci_generic_fill_info, |
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| 212 | us2i_read, |
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| 213 | us2i_write, |
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| 214 | NULL, /* init_dev */ |
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| 215 | NULL /* cleanup_dev */ |
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| 216 | }; |