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Rev | Author | Line No. | Line |
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1301 | jermar | 1 | /* |
2 | * The PCI Library -- Direct Configuration access via i386 Ports |
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3 | * |
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4 | * Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz> |
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5 | * |
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1324 | jermar | 6 | * May 8, 2006 - Modified and ported to HelenOS by Jakub Jermar. |
1301 | jermar | 7 | * |
8 | * Can be freely distributed and used under the terms of the GNU GPL. |
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9 | */ |
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10 | |||
11 | #include <unistd.h> |
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4204 | trochtova | 12 | #include <ddi.h> |
13 | #include <libarch/ddi.h> |
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1301 | jermar | 14 | |
15 | #include "internal.h" |
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16 | |||
4221 | trochtova | 17 | #define PCI_CONF1 0xcf8 |
18 | #define PCI_CONF1_SIZE 8 |
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1301 | jermar | 19 | |
4221 | trochtova | 20 | |
1302 | jermar | 21 | static void conf12_init(struct pci_access *a) |
4221 | trochtova | 22 | { |
1301 | jermar | 23 | } |
24 | |||
1302 | jermar | 25 | static void conf12_cleanup(struct pci_access *a UNUSED) |
1301 | jermar | 26 | { |
27 | } |
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28 | |||
29 | /* |
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30 | * Before we decide to use direct hardware access mechanisms, we try to do some |
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31 | * trivial checks to ensure it at least _seems_ to be working -- we just test |
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32 | * whether bus 00 contains a host bridge (this is similar to checking |
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33 | * techniques used in XFree86, but ours should be more reliable since we |
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34 | * attempt to make use of direct access hints provided by the PCI BIOS). |
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35 | * |
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36 | * This should be close to trivial, but it isn't, because there are buggy |
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37 | * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID. |
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38 | */ |
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39 | |||
1302 | jermar | 40 | static int intel_sanity_check(struct pci_access *a, struct pci_methods *m) |
1301 | jermar | 41 | { |
1302 | jermar | 42 | struct pci_dev d; |
1301 | jermar | 43 | |
1302 | jermar | 44 | a->debug("...sanity check"); |
45 | d.bus = 0; |
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46 | d.func = 0; |
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47 | for (d.dev = 0; d.dev < 32; d.dev++) { |
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48 | u16 class, vendor; |
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1307 | jermar | 49 | if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class, |
1302 | jermar | 50 | sizeof(class)) |
51 | && (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) |
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52 | || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) |
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53 | || m->read(&d, PCI_VENDOR_ID, (byte *) & vendor, |
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54 | sizeof(vendor)) |
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55 | && (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) |
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56 | || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) { |
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57 | a->debug("...outside the Asylum at 0/%02x/0", |
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58 | d.dev); |
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59 | return 1; |
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60 | } |
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1301 | jermar | 61 | } |
1302 | jermar | 62 | a->debug("...insane"); |
63 | return 0; |
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1301 | jermar | 64 | } |
65 | |||
66 | /* |
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67 | * Configuration type 1 |
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68 | */ |
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69 | |||
70 | #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3)) |
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71 | |||
1302 | jermar | 72 | static int conf1_detect(struct pci_access *a) |
1301 | jermar | 73 | { |
1302 | jermar | 74 | unsigned int tmp; |
75 | int res = 0; |
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4221 | trochtova | 76 | |
77 | /* |
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78 | * Gain control over PCI configuration ports. |
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79 | */ |
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80 | void * addr; |
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81 | if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) { |
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82 | return 0; |
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83 | } |
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1301 | jermar | 84 | |
4204 | trochtova | 85 | pio_write_8(0xCFB, 0x01); |
86 | tmp = pio_read_32(0xCF8); |
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87 | pio_write_32(0xCF8, 0x80000000); |
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88 | if (pio_read_32(0xCF8) == 0x80000000) { |
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1302 | jermar | 89 | res = 1; |
4204 | trochtova | 90 | } |
91 | pio_write_32(0xCF8, tmp); |
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92 | if (res) { |
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1302 | jermar | 93 | res = intel_sanity_check(a, &pm_intel_conf1); |
4204 | trochtova | 94 | } |
1302 | jermar | 95 | return res; |
1301 | jermar | 96 | } |
97 | |||
1302 | jermar | 98 | static int conf1_read(struct pci_dev *d, int pos, byte * buf, int len) |
1301 | jermar | 99 | { |
1302 | jermar | 100 | int addr = 0xcfc + (pos & 3); |
1301 | jermar | 101 | |
1302 | jermar | 102 | if (pos >= 256) |
103 | return 0; |
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1301 | jermar | 104 | |
4204 | trochtova | 105 | pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) | |
106 | (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3)); |
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1301 | jermar | 107 | |
1302 | jermar | 108 | switch (len) { |
109 | case 1: |
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4204 | trochtova | 110 | buf[0] = pio_read_8(addr); |
1302 | jermar | 111 | break; |
112 | case 2: |
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4204 | trochtova | 113 | ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr)); |
1302 | jermar | 114 | break; |
115 | case 4: |
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4204 | trochtova | 116 | ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr)); |
1302 | jermar | 117 | break; |
118 | default: |
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119 | return pci_generic_block_read(d, pos, buf, len); |
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120 | } |
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121 | return 1; |
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1301 | jermar | 122 | } |
123 | |||
1302 | jermar | 124 | static int conf1_write(struct pci_dev *d, int pos, byte * buf, int len) |
1301 | jermar | 125 | { |
1302 | jermar | 126 | int addr = 0xcfc + (pos & 3); |
1301 | jermar | 127 | |
1302 | jermar | 128 | if (pos >= 256) |
129 | return 0; |
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1301 | jermar | 130 | |
4204 | trochtova | 131 | pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) | |
132 | (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3)); |
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1301 | jermar | 133 | |
1302 | jermar | 134 | switch (len) { |
135 | case 1: |
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4204 | trochtova | 136 | pio_write_8(addr, buf[0]); |
1302 | jermar | 137 | break; |
138 | case 2: |
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4204 | trochtova | 139 | pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0])); |
1302 | jermar | 140 | break; |
141 | case 4: |
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4204 | trochtova | 142 | pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0])); |
1302 | jermar | 143 | break; |
144 | default: |
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145 | return pci_generic_block_write(d, pos, buf, len); |
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146 | } |
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147 | return 1; |
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1301 | jermar | 148 | } |
149 | |||
150 | /* |
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151 | * Configuration type 2. Obsolete and brain-damaged, but existing. |
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152 | */ |
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153 | |||
1302 | jermar | 154 | static int conf2_detect(struct pci_access *a) |
1301 | jermar | 155 | { |
4221 | trochtova | 156 | /* |
157 | * Gain control over PCI configuration ports. |
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158 | */ |
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159 | void * addr; |
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160 | if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) { |
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161 | return 0; |
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162 | } |
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163 | if (pio_enable((void *)0xC000, 0x1000, &addr)) { |
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164 | return 0; |
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165 | } |
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166 | |||
1302 | jermar | 167 | /* This is ugly and tends to produce false positives. Beware. */ |
4204 | trochtova | 168 | pio_write_8(0xCFB, 0x00); |
169 | pio_write_8(0xCF8, 0x00); |
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170 | pio_write_8(0xCFA, 0x00); |
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171 | if (pio_read_8(0xCF8) == 0x00 && pio_read_8(0xCFA) == 0x00) |
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1302 | jermar | 172 | return intel_sanity_check(a, &pm_intel_conf2); |
173 | else |
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174 | return 0; |
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1301 | jermar | 175 | } |
176 | |||
1302 | jermar | 177 | static int conf2_read(struct pci_dev *d, int pos, byte * buf, int len) |
1301 | jermar | 178 | { |
1302 | jermar | 179 | int addr = 0xc000 | (d->dev << 8) | pos; |
1301 | jermar | 180 | |
1302 | jermar | 181 | if (pos >= 256) |
182 | return 0; |
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1301 | jermar | 183 | |
1302 | jermar | 184 | if (d->dev >= 16) |
185 | /* conf2 supports only 16 devices per bus */ |
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186 | return 0; |
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4204 | trochtova | 187 | pio_write_8(0xcf8, (d->func << 1) | 0xf0); |
188 | pio_write_8(0xcfa, d->bus); |
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1302 | jermar | 189 | switch (len) { |
190 | case 1: |
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4204 | trochtova | 191 | buf[0] = pio_read_8(addr); |
1302 | jermar | 192 | break; |
193 | case 2: |
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4204 | trochtova | 194 | ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr)); |
1302 | jermar | 195 | break; |
196 | case 4: |
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4204 | trochtova | 197 | ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr)); |
1302 | jermar | 198 | break; |
199 | default: |
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4204 | trochtova | 200 | pio_write_8(0xcf8, 0); |
1302 | jermar | 201 | return pci_generic_block_read(d, pos, buf, len); |
202 | } |
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4221 | trochtova | 203 | pio_write_8(0xcf8, 0); |
1302 | jermar | 204 | return 1; |
1301 | jermar | 205 | } |
206 | |||
1302 | jermar | 207 | static int conf2_write(struct pci_dev *d, int pos, byte * buf, int len) |
1301 | jermar | 208 | { |
1302 | jermar | 209 | int addr = 0xc000 | (d->dev << 8) | pos; |
1301 | jermar | 210 | |
1302 | jermar | 211 | if (pos >= 256) |
212 | return 0; |
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1301 | jermar | 213 | |
1302 | jermar | 214 | if (d->dev >= 16) |
1307 | jermar | 215 | d->access->error("conf2_write: only first 16 devices exist."); |
4204 | trochtova | 216 | pio_write_8(0xcf8, (d->func << 1) | 0xf0); |
217 | pio_write_8(0xcfa, d->bus); |
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1302 | jermar | 218 | switch (len) { |
219 | case 1: |
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4204 | trochtova | 220 | pio_write_8(addr, buf[0]); |
1302 | jermar | 221 | break; |
222 | case 2: |
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4204 | trochtova | 223 | pio_write_16(addr, le16_to_cpu(*(u16 *) buf)); |
1302 | jermar | 224 | break; |
225 | case 4: |
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4204 | trochtova | 226 | pio_write_32(addr, le32_to_cpu(*(u32 *) buf)); |
1302 | jermar | 227 | break; |
228 | default: |
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4204 | trochtova | 229 | pio_write_8(0xcf8, 0); |
1302 | jermar | 230 | return pci_generic_block_write(d, pos, buf, len); |
231 | } |
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4204 | trochtova | 232 | pio_write_8(0xcf8, 0); |
1302 | jermar | 233 | return 1; |
1301 | jermar | 234 | } |
235 | |||
236 | struct pci_methods pm_intel_conf1 = { |
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1302 | jermar | 237 | "Intel-conf1", |
238 | NULL, /* config */ |
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239 | conf1_detect, |
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240 | conf12_init, |
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241 | conf12_cleanup, |
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242 | pci_generic_scan, |
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243 | pci_generic_fill_info, |
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244 | conf1_read, |
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245 | conf1_write, |
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246 | NULL, /* init_dev */ |
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247 | NULL /* cleanup_dev */ |
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1301 | jermar | 248 | }; |
249 | |||
250 | struct pci_methods pm_intel_conf2 = { |
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1302 | jermar | 251 | "Intel-conf2", |
252 | NULL, /* config */ |
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253 | conf2_detect, |
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254 | conf12_init, |
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255 | conf12_cleanup, |
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256 | pci_generic_scan, |
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257 | pci_generic_fill_info, |
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258 | conf2_read, |
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259 | conf2_write, |
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260 | NULL, /* init_dev */ |
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261 | NULL /* cleanup_dev */ |
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1301 | jermar | 262 | }; |