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| 1 | jermar | 1 | /* |
| 2 | * Copyright (C) 2001-2004 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 11 | jermar | 29 | #ifndef __ia32_ASM_H__ |
| 30 | #define __ia32_ASM_H__ |
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| 1 | jermar | 31 | |
| 32 | #include <arch/types.h> |
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| 33 | #include <typedefs.h> |
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| 34 | #include <mm/page.h> |
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| 35 | #include <synch/spinlock.h> |
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| 36 | |||
| 37 | extern __u32 interrupt_handler_size; |
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| 38 | |||
| 39 | extern void paging_on(void); |
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| 40 | |||
| 41 | extern void interrupt_handlers(void); |
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| 42 | |||
| 43 | extern __u8 inb(int port); |
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| 44 | extern __u16 inw(int port); |
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| 45 | extern __u32 inl(int port); |
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| 46 | |||
| 47 | extern void outb(int port, __u8 b); |
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| 48 | extern void outw(int port, __u16 w); |
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| 49 | extern void outl(int port, __u32 l); |
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| 50 | |||
| 51 | extern void enable_l_apic_in_msr(void); |
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| 52 | |||
| 115 | jermar | 53 | /** Halt CPU |
| 54 | * |
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| 55 | * Halt the current CPU until interrupt event. |
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| 56 | */ |
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| 57 | static inline void cpu_halt(void) { __asm__("hlt"); }; |
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| 58 | static inline void cpu_sleep(void) { __asm__("hlt"); }; |
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| 1 | jermar | 59 | |
| 115 | jermar | 60 | /** Read CR2 |
| 61 | * |
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| 62 | * Return value in CR2 |
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| 63 | * |
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| 64 | * @return Value read. |
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| 65 | */ |
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| 66 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0" : "=r" (v)); return v; } |
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| 27 | jermar | 67 | |
| 115 | jermar | 68 | /** Write CR3 |
| 69 | * |
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| 70 | * Write value to CR3. |
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| 71 | * |
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| 72 | * @param v Value to be written. |
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| 73 | */ |
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| 74 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
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| 38 | jermar | 75 | |
| 115 | jermar | 76 | /** Read CR3 |
| 77 | * |
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| 78 | * Return value in CR3 |
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| 79 | * |
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| 80 | * @return Value read. |
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| 81 | */ |
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| 82 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; } |
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| 83 | |||
| 84 | /** Write DR0 |
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| 85 | * |
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| 86 | * Write value to DR0. |
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| 87 | * |
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| 88 | * @param v Value to be written. |
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| 89 | */ |
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| 90 | static inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); } |
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| 91 | |||
| 92 | /** Read DR0 |
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| 93 | * |
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| 94 | * Return value in DR0 |
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| 95 | * |
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| 96 | * @return Value read. |
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| 97 | */ |
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| 98 | static inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; } |
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| 99 | |||
| 100 | /** Set priority level low |
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| 101 | * |
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| 102 | * Enable interrupts and return previous |
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| 103 | * value of EFLAGS. |
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| 104 | */ |
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| 105 | static inline pri_t cpu_priority_low(void) { |
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| 106 | pri_t v; |
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| 107 | __asm__ volatile ( |
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| 108 | "pushf\n" |
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| 109 | "popl %0\n" |
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| 110 | "sti\n" |
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| 111 | : "=r" (v) |
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| 112 | ); |
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| 113 | return v; |
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| 114 | } |
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| 115 | |||
| 116 | /** Set priority level high |
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| 117 | * |
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| 118 | * Disable interrupts and return previous |
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| 119 | * value of EFLAGS. |
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| 120 | */ |
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| 121 | static inline pri_t cpu_priority_high(void) { |
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| 122 | pri_t v; |
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| 123 | __asm__ volatile ( |
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| 124 | "pushf\n" |
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| 125 | "popl %0\n" |
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| 126 | "cli\n" |
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| 127 | : "=r" (v) |
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| 128 | ); |
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| 129 | return v; |
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| 130 | } |
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| 131 | |||
| 132 | /** Restore priority level |
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| 133 | * |
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| 134 | * Restore EFLAGS. |
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| 135 | */ |
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| 136 | static inline void cpu_priority_restore(pri_t pri) { |
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| 137 | __asm__ volatile ( |
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| 138 | "pushl %0\n" |
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| 139 | "popf\n" |
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| 140 | : : "r" (pri) |
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| 141 | ); |
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| 142 | } |
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| 143 | |||
| 144 | /** Return raw priority level |
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| 145 | * |
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| 146 | * Return EFLAFS. |
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| 147 | */ |
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| 148 | static inline pri_t cpu_priority_read(void) { |
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| 149 | pri_t v; |
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| 150 | __asm__ volatile ( |
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| 151 | "pushf\n" |
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| 152 | "popl %0\n" |
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| 153 | : "=r" (v) |
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| 154 | ); |
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| 155 | return v; |
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| 156 | } |
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| 157 | |||
| 1 | jermar | 158 | #endif |