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2278 | jancik | 1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32mm |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | */ |
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34 | #include <panic.h> |
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35 | #include <arch/exception.h> |
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36 | #include <arch/debug_print/print.h> |
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37 | #include <arch/mm/page_fault.h> |
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38 | #include <mm/as.h> |
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39 | #include <genarch/mm/page_pt.h> |
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40 | #include <arch.h> |
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41 | |||
42 | |||
43 | //TODO: remove in final version |
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44 | static void print_istate(istate_t* istate); |
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45 | static void print_istate(istate_t* istate) { |
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46 | dprintf("\nIstate dump:\n"); |
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47 | dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3); |
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48 | dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7); |
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49 | dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11); |
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50 | dprintf(" r12:%X sp:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr); |
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51 | } |
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52 | |||
53 | /** |
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54 | * \return Value stored in fault status register |
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55 | */ |
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56 | static inline fault_status_t read_fault_status_register() { |
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57 | fault_status_union_t tmp; |
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58 | asm volatile ( |
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59 | "mrc p15, 0, %0, c5, c0, 0" |
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60 | : "=r"(tmp.dummy) |
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61 | ); |
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62 | return tmp.fsr; |
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63 | } |
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64 | |||
65 | /** |
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66 | * \return Virtual adress. Access on this addres caused exception |
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67 | */ |
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68 | static inline uintptr_t read_fault_address_register() { |
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69 | uintptr_t tmp; |
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70 | // Fault adress is stored in coprocessor15, register 6 |
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71 | asm volatile ( |
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72 | "mrc p15, 0, %0, c6, c0, 0" |
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73 | : "=r"(tmp) |
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74 | ); |
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75 | return tmp; |
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76 | }; |
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77 | |||
78 | /** Check type of instruction |
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79 | * \param i_code Instruction op code |
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80 | * \return true if instruction is load or store, false otherwise |
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81 | */ |
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82 | static inline bool load_store_instruction(instruction_t i_code) { |
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83 | |||
84 | // load store immediate offset |
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85 | if (i_code.instr_type == 0x2) { |
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86 | return true; |
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87 | }; |
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88 | |||
89 | // load store register offset |
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90 | if (i_code.instr_type == 0x3 && i_code.bit4 == 0) { |
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91 | return true; |
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92 | }; |
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93 | |||
94 | // load store multiple |
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95 | if (i_code.instr_type == 0x4) { |
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96 | return true; |
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97 | }; |
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98 | |||
99 | // coprocessor load / strore |
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100 | if (i_code.instr_type == 0x6) { |
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101 | return true; |
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102 | }; |
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103 | |||
104 | return false; |
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105 | } |
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106 | |||
107 | /** Check type of instruction |
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108 | * \param i_code Instruction op code |
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109 | * \return true if instruction is swap, false otherwise |
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110 | */ |
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111 | static inline bool swap_instruction(instruction_t i_code) { |
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112 | |||
113 | // swap, swapb instruction |
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114 | if (i_code.instr_type == 0x0 && |
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115 | (i_code.opcode == 0x8 || i_code.opcode == 0xA) && |
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116 | i_code.access == 0x0 && i_code.bits567 == 0x4 && |
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117 | i_code.bit4 == 1) { |
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118 | return true; |
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119 | }; |
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120 | |||
121 | return false; |
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122 | } |
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123 | |||
124 | |||
125 | /** |
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126 | * Decode instruction and decide if try to read or write into memmory. |
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127 | * |
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128 | * \param instr_addr address of instruction which attempts access into memmory |
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129 | * \param badvaddr Virtual address on which instruction tries to access |
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130 | * \return type of access into memmory |
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131 | * Note: return PF_ACESS_EXEC if no memmory acess |
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132 | */ |
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133 | //TODO: remove debug print in final version ... instead panic return PF_ACESS_EXEC |
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134 | static pf_access_t get_memmory_access_type(uint32_t instr_addr, uintptr_t badvaddr) { |
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135 | instruction_union_t tmp; |
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136 | tmp.ip = instr_addr; |
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137 | // get instruction op code |
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138 | instruction_t i_code = *(tmp.instr); |
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139 | |||
140 | dprintf("get_instruction_memmory_access\n"); |
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141 | dprintf(" instr_addr:%X\n",instr_addr); |
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142 | dprintf(" i_code:%X\n",i_code); |
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143 | dprintf(" i_code.condition:%d\n", i_code.condition); |
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144 | dprintf(" i_code.instr_type:%d\n",i_code.instr_type); |
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145 | dprintf(" i_code.opcode:%d\n",i_code.opcode); |
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146 | dprintf(" i_code.acess:%d\n", i_code.access); |
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147 | dprintf(" i_code.dummy:%d\n", i_code.dummy); |
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148 | dprintf(" i_code.bits567%d\n", i_code.bits567); |
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149 | dprintf(" i_code.bit4:%d\n", i_code.bit4); |
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150 | dprintf(" i_code.dummy1:%d\n", i_code.dummy1); |
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151 | |||
152 | |||
153 | // undefined instructions ... (or special instructions) |
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154 | if (i_code.condition == 0xf) { |
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155 | panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
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156 | return PF_ACCESS_EXEC; |
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157 | }; |
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158 | |||
159 | // load store instructions |
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160 | if (load_store_instruction(i_code)) { |
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161 | if ( i_code.access == 1) { |
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162 | return PF_ACCESS_READ; |
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163 | } else { |
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164 | return PF_ACCESS_WRITE; |
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165 | } |
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166 | }; |
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167 | |||
168 | // swap, swpb instruction |
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169 | if (swap_instruction(i_code)) |
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170 | { |
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171 | /* Swap instructions make read and write in one step. |
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172 | * Type of access that caused exception have to page tables |
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173 | * and access rights. |
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174 | */ |
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175 | //TODO: ALF!!!!! cann't use AS as is define as THE->as and THE structure is sored after stack_base of current thread |
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176 | // but now ... in exception we have separate stacks <==> different stack_pointer ... so AS contains nonsence data |
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177 | // same case as_page_fault .... it's nessesary to solve "stack" problem |
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178 | pte_level1_t* pte = (pte_level1_t*) |
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179 | pt_mapping_operations.mapping_find(AS, badvaddr); |
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180 | |||
181 | ASSERT(pte); |
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182 | |||
183 | /* check if read possible |
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184 | * Note: Don't check PTE_READABLE because it returns 1 everytimes */ |
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185 | if ( !PTE_PRESENT(pte) ) { |
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186 | return PF_ACCESS_READ; |
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187 | } |
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188 | if ( !PTE_WRITABLE(pte) ) { |
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189 | return PF_ACCESS_WRITE; |
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190 | } |
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191 | else |
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192 | // badvaddr is present readable and writeable but error occured ... why? |
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193 | panic("page_fault - swap instruction, but address readable and writeable (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
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194 | } |
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195 | panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
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196 | return PF_ACCESS_EXEC; |
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197 | } |
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198 | |||
199 | /** |
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200 | * Routine that solves exception data_abourt |
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201 | * ... you try to load or store value into invalid memmory address |
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202 | * \param istate State of CPU when data abourt occured |
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203 | * \param n number of exception |
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204 | */ |
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205 | //TODO: remove debug prints in final tested version |
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206 | void data_abort(int n, istate_t *istate) { |
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207 | fault_status_t fsr = read_fault_status_register(); |
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208 | uintptr_t page = read_fault_address_register(); |
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209 | |||
210 | pf_access_t access = get_memmory_access_type( istate->lr, page); |
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211 | |||
212 | print_istate(istate); |
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213 | dprintf(" page fault : ip:%X, va:%X, status:%x(%x), access:%d\n", istate->lr, page, fsr.status,fsr, access); |
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214 | |||
215 | /* Alf: Will be commented until stack problem will be solved ... |
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216 | as_page_fault make consequent page faults |
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217 | |||
218 | int ret = as_page_fault(page, access, istate); |
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219 | dprintf(" as_page_fault ret:%d\n", ret); |
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220 | if (ret == AS_PF_FAULT) { |
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221 | fault_if_from_uspace(istate, "Page fault: %#x", page); |
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222 | |||
223 | panic("page fault\n"); |
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224 | } |
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225 | */ |
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226 | // TODO: Remove this ... now for testing purposes ... it's bad to test page faults in kernel, where no page faults should occures |
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227 | panic("page fault ... solved\n"); |
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228 | |||
229 | } |
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230 | |||
231 | /** |
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232 | * Routine that solves exception prefetch_about |
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233 | * ... you try to execute instruction on invalid address |
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234 | * \param istate State of CPU when prefetch abourt occured |
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235 | * \param n number of exception |
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236 | */ |
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237 | void prefetch_abort(int n, istate_t *istate) { |
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238 | // Prefetch can be made be bkpt instruction |
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239 | print_istate(istate); |
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240 | dprintf(" prefetch_abourt ... instruction on adress:%x can't be fetched\n", istate->lr); |
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241 | |||
242 | /* Alf: Will be commented until stack problem will be solved ... |
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243 | as_page_fault make consequent page faults |
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244 | |||
245 | int ret = as_page_fault(istate->lr, PF_ACCESS_EXEC, istate); |
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246 | dprintf(" as_page_fault ret:%d\n", ret); |
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247 | if (ret == AS_PF_FAULT) { |
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248 | panic("page fault - instruction fetch at addr:%X\n", istate->lr); |
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249 | } |
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250 | */ |
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251 | |||
252 | panic("Prefetch abourt ... solved"); |
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253 | } |
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254 | |||
255 | /** @} |
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256 | */ |
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257 |