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2128 | jermar | 1 | /* |
2238 | kebrt | 2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2128 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32mm |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
35 | #include <arch/mm/page.h> |
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36 | #include <genarch/mm/page_pt.h> |
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2258 | jancik | 37 | #include <arch.h> |
2128 | jermar | 38 | #include <mm/page.h> |
2182 | jancik | 39 | #include <align.h> |
40 | #include <config.h> |
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2258 | jancik | 41 | #include <arch/exception.h> |
42 | #include <typedefs.h> |
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43 | #include <arch/types.h> |
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44 | #include <interrupt.h> |
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45 | |||
46 | //TODO: remove in final version |
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2182 | jancik | 47 | #include "../aux_print/printf.h" |
2128 | jermar | 48 | |
2258 | jancik | 49 | |
50 | // localy used types |
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51 | /** |
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52 | * Decribes structure of fault status register in coprocessor 15 |
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53 | */ |
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54 | typedef struct { |
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55 | unsigned status : 3; |
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56 | unsigned domain : 4; |
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57 | unsigned zero : 1; |
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58 | unsigned should_be_zero : 24; |
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59 | } __attribute__ ((packed)) fault_status_t; |
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60 | |||
61 | /** |
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62 | * Help union used for overcasting integer value into fault_status_t type |
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63 | */ |
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64 | typedef union { |
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65 | fault_status_t fsr; |
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66 | uint32_t dummy; |
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67 | } fault_status_union_t; |
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68 | |||
69 | /** |
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70 | * Very simplyfied description of instruction code structure intended for |
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71 | * recognising memmory access of instruction ( reads or writes into memmory) |
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72 | * more details: see ARM architecture preference chapter:3.1 Instruction set encoding |
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73 | */ |
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74 | typedef struct { |
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75 | unsigned dummy1 : 4; |
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76 | unsigned bit4 : 1; |
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77 | unsigned bits567 : 3; |
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78 | unsigned dummy : 12; |
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79 | unsigned access : 1; |
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80 | unsigned opcode : 4; |
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81 | unsigned instr_type : 3; |
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82 | unsigned condition : 4; |
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83 | } __attribute__ ((packed)) instruction_t; |
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84 | |||
85 | /** |
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86 | * Help union used for overcasting ip register (uint_32_t) value into instruction_t pointer |
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87 | */ |
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88 | typedef union { |
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89 | instruction_t* instr; |
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90 | uint32_t ip; |
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91 | } instruction_union_t; |
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92 | |||
93 | // localy used functions |
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94 | static fault_status_t read_fault_status_register(); |
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95 | static uintptr_t read_fault_address_register(); |
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96 | static pf_access_t get_memmory_access_type(uint32_t instr_addr, uintptr_t badvaddr); |
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97 | |||
98 | |||
99 | /** |
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100 | * Initializes kernel adress space page tables, sets abourts exceptions vectors |
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101 | */ |
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2128 | jermar | 102 | void page_arch_init(void) |
103 | { |
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2238 | kebrt | 104 | uintptr_t cur; |
2182 | jancik | 105 | int flags; |
106 | |||
2128 | jermar | 107 | page_mapping_operations = &pt_mapping_operations; |
2182 | jancik | 108 | |
109 | flags = PAGE_CACHEABLE; |
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2238 | kebrt | 110 | |
2243 | kebrt | 111 | /* PA2KA(identity) mapping for all frames until last_frame */ |
112 | for (cur = 0; cur < last_frame; cur += FRAME_SIZE) { |
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113 | page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags); |
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114 | } |
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115 | |||
2256 | kebrt | 116 | // TODO: move to the kernel space |
117 | page_mapping_insert(AS_KERNEL, 0x00000000, 0x00000000, flags); |
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2263 | kebrt | 118 | // TODO: remove when aux_printf not needed |
2256 | kebrt | 119 | page_mapping_insert(AS_KERNEL, 0x10000000, 0x10000000, flags); |
120 | |||
2263 | kebrt | 121 | exc_register(EXC_DATA_ABORT, "page_fault data abort", (iroutine) data_abourt); |
122 | exc_register(EXC_PREFETCH_ABORT, "page_fault prefetch abort", (iroutine) prefetch_abourt); |
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2256 | kebrt | 123 | |
2263 | kebrt | 124 | as_switch(NULL, AS_KERNEL); |
2258 | jancik | 125 | |
2243 | kebrt | 126 | // TODO: register fault routine |
2128 | jermar | 127 | } |
128 | |||
2258 | jancik | 129 | /** |
130 | * Map device into kernel space. |
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131 | * |
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132 | * This function adds mapping of physical address that is read/write only |
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133 | * from kernel and not bufferable. |
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134 | * |
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135 | * \param physaddr Physical addres where device is connected |
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136 | * \param size Length of area where device is present |
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137 | * \return Virtual address where device will be accessable |
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138 | * Note: This is copy of IA32 hw_map code |
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139 | */ |
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2128 | jermar | 140 | uintptr_t hw_map(uintptr_t physaddr, size_t size) |
141 | { |
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2258 | jancik | 142 | if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) |
143 | panic("Unable to map physical memory %p (%d bytes)", physaddr, size) |
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144 | |||
145 | uintptr_t virtaddr = PA2KA(last_frame); |
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146 | pfn_t i; |
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147 | for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) |
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148 | page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE | PAGE_READ | PAGE_WRITE | PAGE_KERNEL); |
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149 | |||
150 | last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE); |
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151 | |||
152 | return virtaddr; |
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2128 | jermar | 153 | } |
154 | |||
2258 | jancik | 155 | //TODO: remove in final version |
156 | static void print_istate(istate_t* istate); |
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157 | static void print_istate(istate_t* istate) { |
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158 | aux_printf("\nIstate dump:\n"); |
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159 | aux_printf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3); |
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160 | aux_printf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7); |
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161 | aux_printf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11); |
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162 | aux_printf(" r12:%X sp:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr); |
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163 | } |
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164 | |||
165 | /** |
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166 | * \return Value stored in fault status register |
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167 | */ |
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168 | static fault_status_t read_fault_status_register() { |
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169 | fault_status_union_t tmp; |
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170 | asm volatile ( |
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171 | "mrc p15, 0, %0, c5, c0, 0" |
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172 | : "=r"(tmp.dummy) |
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173 | ); |
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174 | return tmp.fsr; |
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175 | } |
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176 | |||
177 | /** |
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178 | * \return Virtual adress. Access on this addres caused exception |
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179 | */ |
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180 | static uintptr_t read_fault_address_register() { |
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181 | uintptr_t tmp; |
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182 | // Fault adress is stored in coprocessor15, register 6 |
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183 | asm volatile ( |
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184 | "mrc p15, 0, %0, c6, c0, 0" |
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185 | : "=r"(tmp) |
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186 | ); |
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187 | return tmp; |
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188 | }; |
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189 | |||
190 | /** |
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191 | * Decode instruction and decide if try to read or write into memmory. |
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192 | * |
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193 | * \param instr_addr address of instruction which attempts to access into memmory |
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194 | * \param badvaddr Virtual address on which instruction tries to access |
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195 | * \return type of access into memmory |
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196 | * Note: return PF_ACESS_EXEC if no memmory acess |
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197 | */ |
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198 | //TODO: remove debug print in final version ... instead panic return PF_ACESS_EXEC |
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199 | pf_access_t get_memmory_access_type(uint32_t instr_addr, uintptr_t badvaddr) { |
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200 | instruction_union_t tmp; |
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201 | tmp.ip = instr_addr; |
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202 | // get instruction op code |
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203 | instruction_t i_code = *(tmp.instr); |
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204 | |||
205 | aux_printf("get_instruction_memmory_access\n"); |
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206 | aux_printf(" i_code:%X\n",i_code); |
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207 | aux_printf(" i_code.condition:%d\n", i_code.condition); |
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208 | aux_printf(" i_code.instr_type:%d\n",i_code.instr_type); |
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209 | aux_printf(" i_code.opcode:%d\n",i_code.opcode); |
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210 | aux_printf(" i_code.acess:%d\n", i_code.access); |
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211 | aux_printf(" i_code.dummy:%d\n", i_code.dummy); |
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212 | aux_printf(" i_code.bits567%d\n", i_code.bits567); |
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213 | aux_printf(" i_code.bit4:%d\n", i_code.bit4); |
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214 | aux_printf(" i_code.dummy1:%d\n", i_code.dummy1); |
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215 | |||
216 | |||
217 | // undefined instructions ... (or special instructions) |
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218 | if ( i_code.condition == 0xf ) { |
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219 | panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
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220 | return PF_ACCESS_EXEC; |
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221 | } |
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222 | |||
223 | // load store instructions |
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224 | if ( ( i_code.instr_type == 0x2 ) || // load store immediate offset |
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225 | ( i_code.instr_type == 0x3 && i_code.bit4 == 0) || // load store register offset |
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226 | ( i_code.instr_type == 0x4 ) || // load store multiple |
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227 | ( i_code.instr_type == 0x6 ) // coprocessor load / strore |
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228 | ) { |
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229 | if ( i_code.access == 1) { |
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230 | return PF_ACCESS_READ; |
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231 | } else { |
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232 | return PF_ACCESS_WRITE; |
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233 | } |
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234 | }; |
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235 | |||
236 | // swap, swpb instruction |
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237 | if ( i_code.instr_type == 0x0 && (i_code.opcode == 0x8 || i_code.opcode == 0xA) && |
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238 | i_code.access == 0x0 && i_code.bits567 == 0x4 && i_code.bit4 == 1 ) |
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239 | { |
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240 | /* Swap instructions make read and write in one step. |
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241 | * Type of access that caused exception have to page tables and access rights. |
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242 | */ |
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243 | //TODO: ALF!!!!! cann't use AS as is define as THE->as and THE structure is sored after stack_base of current thread |
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244 | // but now ... in exception we have separate stacks <==> different stack_pointer ... so AS contains nonsence data |
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245 | // same case as_page_fault .... it's nessesary to solve "stack" problem |
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246 | pte_level1_t* pte = (pte_level1_t*)pt_mapping_operations.mapping_find(AS, badvaddr); |
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247 | |||
248 | ASSERT(pte); |
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249 | |||
250 | /* check if read possible |
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251 | * Note: Don't check PTE_READABLE because it returns 1 everytimes */ |
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252 | if ( !PTE_PRESENT(pte) ) { |
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253 | return PF_ACCESS_READ; |
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254 | } |
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255 | if ( !PTE_WRITABLE(pte) ) { |
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256 | return PF_ACCESS_WRITE; |
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257 | } |
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258 | else |
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259 | // badvaddr is present readable and writeable but error occured ... why? |
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260 | panic("page_fault - swap instruction, but address readable and writeable (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
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261 | } |
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262 | panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
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263 | return PF_ACCESS_EXEC; |
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264 | } |
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265 | |||
266 | /** |
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267 | * Routine that solves exception data_abourt |
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268 | * ... you try to load or store value into invalid memmory address |
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269 | * \param istate State of CPU when data abourt occured |
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270 | * \param n number of exception |
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271 | */ |
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272 | //TODO: remove debug prints in final tested version |
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273 | void data_abourt(int n, istate_t *istate) { |
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274 | fault_status_t fsr = read_fault_status_register(); |
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275 | uintptr_t page = read_fault_address_register(); |
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276 | |||
277 | pf_access_t access = get_memmory_access_type( istate->lr, page); |
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278 | |||
279 | print_istate(istate); |
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280 | aux_printf(" page fault : ip:%X, va:%X, status:%x(%x), access:%d\n", istate->lr, page, fsr.status,fsr, access); |
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281 | |||
282 | int ret = as_page_fault(page, access, istate); |
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283 | aux_printf(" as_page_fault ret:%d\n", ret); |
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284 | if (ret == AS_PF_FAULT) { |
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285 | fault_if_from_uspace(istate, "Page fault: %#x", page); |
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286 | |||
287 | panic("page fault\n"); |
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288 | } |
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289 | |||
290 | // TODO: Remove this ... now for testing purposes ... it's bad to test page faults in kernel, where no page faults should occures |
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291 | panic("page fault ... solved\n"); |
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292 | |||
293 | } |
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294 | |||
295 | /** |
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296 | * Routine that solves exception prefetch_about |
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297 | * ... you try to execute instruction on invalid address |
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298 | * \param istate State of CPU when prefetch abourt occured |
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299 | * \param n number of exception |
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300 | */ |
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301 | void prefetch_abourt(int n, istate_t *istate) { |
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302 | // Prefetch can be made be bkpt instruction |
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303 | print_istate(istate); |
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304 | aux_printf(" prefetch_abourt ... instruction on adress:%x can't be fetched\n", istate->lr); |
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305 | |||
306 | int ret = as_page_fault(istate->lr, PF_ACCESS_EXEC, istate); |
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307 | aux_printf(" as_page_fault ret:%d\n", ret); |
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308 | if (ret == AS_PF_FAULT) { |
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309 | panic("page fault - instruction fetch at addr:%X\n", istate->lr); |
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310 | } |
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311 | |||
312 | panic("Prefetch abourt ... solved"); |
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313 | } |
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314 | |||
2128 | jermar | 315 | /** @} |
316 | */ |
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2182 | jancik | 317 |