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2235 | stepan | 1 | /* |
2179 | stepan | 2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32 |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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2410 | stepan | 33 | * @brief Exception handlers and exception initialization routines. |
2179 | stepan | 34 | */ |
35 | |||
2329 | kebrt | 36 | |
2179 | stepan | 37 | #include <arch/exception.h> |
2326 | kebrt | 38 | #include <arch/debug/print.h> |
2179 | stepan | 39 | #include <arch/memstr.h> |
2235 | stepan | 40 | #include <arch/regutils.h> |
41 | #include <interrupt.h> |
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2306 | kebrt | 42 | #include <arch/machine.h> |
2282 | jancik | 43 | #include <arch/mm/page_fault.h> |
2284 | stepan | 44 | #include <print.h> |
2286 | stepan | 45 | #include <syscall/syscall.h> |
2179 | stepan | 46 | |
2407 | stepan | 47 | /** Offset used in calculation of exception handler's relative address. |
48 | * |
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49 | * @see install_handler() |
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50 | */ |
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51 | #define PREFETCH_OFFSET 0x8 |
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2329 | kebrt | 52 | |
2407 | stepan | 53 | /** LDR instruction's code */ |
2306 | kebrt | 54 | #define LDR_OPCODE 0xe59ff000 |
2179 | stepan | 55 | |
2407 | stepan | 56 | /** Number of exception vectors. */ |
57 | #define EXC_VECTORS 8 |
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2329 | kebrt | 58 | |
2407 | stepan | 59 | /** Size of memory block occupied by exception vectors. */ |
60 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
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61 | |||
62 | |||
2355 | stepan | 63 | /** Switches to kernel stack and saves all registers there. |
64 | * |
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65 | * Temporary exception stack is used to save a few registers |
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66 | * before stack switch takes place. |
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67 | */ |
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2284 | stepan | 68 | inline static void setup_stack_and_save_regs() |
69 | { |
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2344 | stepan | 70 | asm volatile("ldr r13, =exc_stack \n\ |
2284 | stepan | 71 | stmfd r13!, {r0} \n\ |
72 | mrs r0, spsr \n\ |
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73 | and r0, r0, #0x1f \n\ |
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74 | cmp r0, #0x10 \n\ |
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75 | bne 1f \n\ |
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76 | \n\ |
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77 | @prev mode was usermode \n\ |
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78 | ldmfd r13!, {r0} \n\ |
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79 | ldr r13, =supervisor_sp \n\ |
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2298 | stepan | 80 | ldr r13, [r13] \n\ |
2286 | stepan | 81 | stmfd r13!, {lr} \n\ |
82 | stmfd r13!, {r0-r12} \n\ |
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2284 | stepan | 83 | stmfd r13!, {r13, lr}^ \n\ |
84 | mrs r0, spsr \n\ |
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85 | stmfd r13!, {r0} \n\ |
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86 | b 2f \n\ |
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87 | \n\ |
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88 | @prev mode was not usermode \n\ |
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89 | 1: \n\ |
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90 | stmfd r13!, {r1, r2, r3} \n\ |
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91 | mrs r1, cpsr \n\ |
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92 | mov r2, lr \n\ |
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93 | bic r1, r1, #0x1f \n\ |
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94 | orr r1, r1, r0 \n\ |
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95 | mrs r0, cpsr \n\ |
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96 | msr cpsr_c, r1 \n\ |
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97 | \n\ |
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98 | mov r3, r13 \n\ |
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99 | stmfd r13!, {r2} \n\ |
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2286 | stepan | 100 | mov r2, lr \n\ |
2284 | stepan | 101 | stmfd r13!, {r4-r12} \n\ |
102 | mov r1, r13 \n\ |
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2298 | stepan | 103 | @following two lines are for debugging \n\ |
104 | mov sp, #0 \n\ |
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2286 | stepan | 105 | mov lr, #0 \n\ |
2284 | stepan | 106 | msr cpsr_c, r0 \n\ |
107 | \n\ |
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108 | ldmfd r13!, {r4, r5, r6, r7} \n\ |
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109 | stmfd r1!, {r4, r5, r6} \n\ |
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110 | stmfd r1!, {r7} \n\ |
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111 | stmfd r1!, {r2} \n\ |
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112 | stmfd r1!, {r3} \n\ |
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113 | mrs r0, spsr \n\ |
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114 | stmfd r1!, {r0} \n\ |
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115 | mov r13, r1 \n\ |
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116 | 2:" |
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117 | ); |
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118 | } |
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119 | |||
2407 | stepan | 120 | |
2355 | stepan | 121 | /** Returns from exception mode. |
122 | * |
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123 | * Previously saved state of registers (including control register) |
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124 | * is restored from the stack. |
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125 | */ |
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2284 | stepan | 126 | inline static void load_regs() |
127 | { |
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128 | asm volatile( "ldmfd r13!, {r0} \n\ |
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129 | msr spsr, r0 \n\ |
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130 | and r0, r0, #0x1f \n\ |
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131 | cmp r0, #0x10 \n\ |
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132 | bne 3f \n\ |
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133 | \n\ |
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134 | @return to user mode \n\ |
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135 | ldmfd r13!, {r13, lr}^ \n\ |
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136 | b 4f \n\ |
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137 | \n\ |
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138 | @return to non-user mode \n\ |
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139 | 3: \n\ |
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140 | ldmfd r13!, {r1, r2} \n\ |
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141 | mrs r3, cpsr \n\ |
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142 | bic r3, r3, #0x1f \n\ |
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143 | orr r3, r3, r0 \n\ |
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144 | mrs r0, cpsr \n\ |
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145 | msr cpsr_c, r3 \n\ |
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146 | \n\ |
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147 | mov r13, r1 \n\ |
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148 | mov lr, r2 \n\ |
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149 | msr cpsr_c, r0 \n\ |
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150 | \n\ |
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151 | @actual return \n\ |
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2298 | stepan | 152 | 4: ldmfd r13, {r0-r12, pc}^" |
2284 | stepan | 153 | ); |
154 | } |
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155 | |||
2411 | stepan | 156 | |
2407 | stepan | 157 | /** Switch CPU to mode in which interrupts are serviced (currently it |
158 | * is Undefined mode). |
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159 | * |
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160 | * The default mode for interrupt servicing (Interrupt Mode) |
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161 | * can not be used because of nested interrupts (which can occur |
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162 | * because interrupt are enabled in higher levels of interrupt handler). |
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163 | */ |
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2414 | kebrt | 164 | inline static void switch_to_irq_servicing_mode() |
2407 | stepan | 165 | { |
166 | /* switch to Undefined mode */ |
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167 | asm volatile( |
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168 | /* save regs used during switching */ |
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169 | "stmfd sp!, {r0-r3} \n" |
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170 | |||
171 | /* save stack pointer and link register to r1, r2 */ |
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172 | "mov r1, sp \n" |
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173 | "mov r2, lr \n" |
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174 | |||
175 | /* mode switch */ |
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176 | "mrs r0, cpsr \n" |
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177 | "bic r0, r0, #0x1f \n" |
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178 | "orr r0, r0, #0x1b \n" |
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179 | "msr cpsr_c, r0 \n" |
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180 | |||
181 | /* restore saved sp and lr */ |
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182 | "mov sp, r1 \n" |
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183 | "mov lr, r2 \n" |
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184 | |||
185 | /* restore original regs */ |
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186 | "ldmfd sp!, {r0-r3} \n" |
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187 | ); |
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188 | } |
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189 | |||
2411 | stepan | 190 | |
2355 | stepan | 191 | /** Calls exception dispatch routine. */ |
2235 | stepan | 192 | #define CALL_EXC_DISPATCH(exception) \ |
193 | asm("mov r0, %0" : : "i" (exception)); \ |
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2284 | stepan | 194 | asm("mov r1, r13"); \ |
2235 | stepan | 195 | asm("bl exc_dispatch"); |
196 | |||
2407 | stepan | 197 | |
2235 | stepan | 198 | /** General exception handler. |
2355 | stepan | 199 | * |
2235 | stepan | 200 | * Stores registers, dispatches the exception, |
201 | * and finally restores registers and returns from exception processing. |
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2329 | kebrt | 202 | * |
203 | * @param exception Exception number. |
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2235 | stepan | 204 | */ |
205 | #define PROCESS_EXCEPTION(exception) \ |
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2284 | stepan | 206 | setup_stack_and_save_regs(); \ |
2235 | stepan | 207 | CALL_EXC_DISPATCH(exception) \ |
2284 | stepan | 208 | load_regs(); |
2235 | stepan | 209 | |
2284 | stepan | 210 | |
2235 | stepan | 211 | /** Updates specified exception vector to jump to given handler. |
2355 | stepan | 212 | * |
2329 | kebrt | 213 | * Addresses of handlers are stored in memory following exception vectors. |
2235 | stepan | 214 | */ |
215 | static void install_handler (unsigned handler_addr, unsigned* vector) |
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216 | { |
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217 | /* relative address (related to exc. vector) of the word |
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218 | * where handler's address is stored |
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219 | */ |
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220 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
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2179 | stepan | 221 | |
2235 | stepan | 222 | /* make it LDR instruction and store at exception vector */ |
223 | *vector = handler_address_ptr | LDR_OPCODE; |
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2179 | stepan | 224 | |
2235 | stepan | 225 | /* store handler's address */ |
226 | *(vector + EXC_VECTORS) = handler_addr; |
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2284 | stepan | 227 | |
2179 | stepan | 228 | } |
229 | |||
2284 | stepan | 230 | |
2329 | kebrt | 231 | /** Low-level Reset Exception handler. */ |
2235 | stepan | 232 | static void reset_exception_entry() |
233 | { |
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234 | PROCESS_EXCEPTION(EXC_RESET); |
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2179 | stepan | 235 | } |
236 | |||
2329 | kebrt | 237 | |
238 | /** Low-level Software Interrupt Exception handler. */ |
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2235 | stepan | 239 | static void swi_exception_entry() |
240 | { |
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241 | PROCESS_EXCEPTION(EXC_SWI); |
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2179 | stepan | 242 | } |
243 | |||
2329 | kebrt | 244 | |
245 | /** Low-level Undefined Instruction Exception handler. */ |
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2235 | stepan | 246 | static void undef_instr_exception_entry() |
247 | { |
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248 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
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249 | } |
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250 | |||
2329 | kebrt | 251 | |
252 | /** Low-level Fast Interrupt Exception handler. */ |
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2235 | stepan | 253 | static void fiq_exception_entry() |
254 | { |
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255 | PROCESS_EXCEPTION(EXC_FIQ); |
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256 | } |
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257 | |||
2329 | kebrt | 258 | |
259 | /** Low-level Prefetch Abort Exception handler. */ |
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2235 | stepan | 260 | static void prefetch_abort_exception_entry() |
261 | { |
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262 | asm("sub lr, lr, #4"); |
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263 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
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264 | } |
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265 | |||
2329 | kebrt | 266 | |
267 | /** Low-level Data Abort Exception handler. */ |
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2235 | stepan | 268 | static void data_abort_exception_entry() |
269 | { |
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270 | asm("sub lr, lr, #8"); |
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271 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
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272 | } |
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273 | |||
274 | |||
2355 | stepan | 275 | /** Low-level Interrupt Exception handler. |
276 | * |
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277 | * CPU is switched to Undefined mode before further interrupt processing |
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278 | * because of possible occurence of nested interrupt exception, which |
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279 | * would overwrite (and thus spoil) stack pointer. |
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280 | */ |
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2235 | stepan | 281 | static void irq_exception_entry() |
282 | { |
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283 | asm("sub lr, lr, #4"); |
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2344 | stepan | 284 | setup_stack_and_save_regs(); |
2407 | stepan | 285 | |
2414 | kebrt | 286 | switch_to_irq_servicing_mode(); |
2407 | stepan | 287 | |
2344 | stepan | 288 | CALL_EXC_DISPATCH(EXC_IRQ) |
289 | |||
290 | load_regs(); |
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2235 | stepan | 291 | } |
292 | |||
2329 | kebrt | 293 | |
2286 | stepan | 294 | /** Software Interrupt handler. |
295 | * |
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296 | * Dispatches the syscall. |
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297 | */ |
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2304 | kebrt | 298 | static void swi_exception(int exc_no, istate_t *istate) |
2284 | stepan | 299 | { |
2341 | kebrt | 300 | /* |
2304 | kebrt | 301 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
2298 | stepan | 302 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
2341 | kebrt | 303 | */ |
2298 | stepan | 304 | |
2286 | stepan | 305 | istate->r0 = syscall_handler( |
306 | istate->r0, |
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307 | istate->r1, |
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308 | istate->r2, |
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309 | istate->r3, |
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310 | istate->r4); |
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2284 | stepan | 311 | } |
312 | |||
2329 | kebrt | 313 | |
2235 | stepan | 314 | /** Interrupt Exception handler. |
2286 | stepan | 315 | * |
2235 | stepan | 316 | * Determines the sources of interrupt, and calls their handlers. |
317 | */ |
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2304 | kebrt | 318 | static void irq_exception(int exc_no, istate_t *istate) |
2235 | stepan | 319 | { |
2306 | kebrt | 320 | machine_irq_exception(exc_no, istate); |
2235 | stepan | 321 | } |
322 | |||
2329 | kebrt | 323 | |
324 | /** Fills exception vectors with appropriate exception handlers. */ |
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2235 | stepan | 325 | void install_exception_handlers(void) |
326 | { |
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327 | install_handler((unsigned)reset_exception_entry, |
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328 | (unsigned*)EXC_RESET_VEC); |
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329 | |||
330 | install_handler((unsigned)undef_instr_exception_entry, |
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331 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
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332 | |||
333 | install_handler((unsigned)swi_exception_entry, |
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334 | (unsigned*)EXC_SWI_VEC); |
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335 | |||
336 | install_handler((unsigned)prefetch_abort_exception_entry, |
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337 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
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338 | |||
339 | install_handler((unsigned)data_abort_exception_entry, |
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340 | (unsigned*)EXC_DATA_ABORT_VEC); |
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341 | |||
2284 | stepan | 342 | install_handler((unsigned)irq_exception_entry, |
2235 | stepan | 343 | (unsigned*)EXC_IRQ_VEC); |
344 | |||
345 | install_handler((unsigned)fiq_exception_entry, |
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346 | (unsigned*)EXC_FIQ_VEC); |
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2179 | stepan | 347 | } |
348 | |||
2329 | kebrt | 349 | |
2284 | stepan | 350 | #ifdef HIGH_EXCEPTION_VECTORS |
2329 | kebrt | 351 | /** Activates use of high exception vectors addresses. */ |
352 | static void high_vectors() |
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2262 | stepan | 353 | { |
354 | uint32_t control_reg; |
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355 | |||
356 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
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357 | |||
358 | //switch on the high vectors bit |
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359 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
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360 | |||
361 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
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362 | } |
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2284 | stepan | 363 | #endif |
2262 | stepan | 364 | |
2326 | kebrt | 365 | |
2245 | stepan | 366 | /** Initializes exception handling. |
367 | * |
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368 | * Installs low-level exception handlers and then registers |
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369 | * exceptions and their handlers to kernel exception dispatcher. |
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370 | */ |
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2235 | stepan | 371 | void exception_init(void) |
372 | { |
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2262 | stepan | 373 | #ifdef HIGH_EXCEPTION_VECTORS |
374 | high_vectors(); |
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375 | #endif |
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2245 | stepan | 376 | install_exception_handlers(); |
377 | |||
2235 | stepan | 378 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
2277 | jancik | 379 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
380 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
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2284 | stepan | 381 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
2179 | stepan | 382 | } |
383 | |||
2326 | kebrt | 384 | |
385 | /** Prints #istate_t structure content. |
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386 | * |
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387 | * @param istate Structure to be printed. |
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388 | */ |
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2304 | kebrt | 389 | void print_istate(istate_t *istate) |
390 | { |
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391 | dprintf("istate dump:\n"); |
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392 | |||
393 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
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394 | istate->r0, istate->r1, istate->r2, istate->r3); |
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395 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
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396 | istate->r4, istate->r5, istate->r6, istate->r7); |
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397 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
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398 | istate->r8, istate->r9, istate->r10, istate->r11); |
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399 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
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400 | istate->r12, istate->sp, istate->lr, istate->spsr); |
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401 | |||
402 | dprintf(" pc: %x\n", istate->pc); |
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403 | } |
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404 | |||
405 | |||
2179 | stepan | 406 | /** @} |
407 | */ |