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3528 | pillai | 1 | /* |
4629 | pillai | 2 | * Copyright (c) 2009 Vineeth Pillai |
3528 | pillai | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32qemu_icp |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | * @brief QEMU icp drivers. |
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34 | */ |
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35 | |||
36 | #include <interrupt.h> |
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37 | #include <ipc/irq.h> |
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38 | #include <console/chardev.h> |
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39 | #include <arch/drivers/qemu.h> |
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4629 | pillai | 40 | #include <arch/drivers/pl050.h> |
3528 | pillai | 41 | #include <console/console.h> |
42 | #include <sysinfo/sysinfo.h> |
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43 | #include <print.h> |
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44 | #include <ddi/device.h> |
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45 | #include <mm/page.h> |
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4634 | pillai | 46 | #include <mm/frame.h> |
47 | #include <arch/mm/frame.h> |
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3528 | pillai | 48 | #include <arch/machine.h> |
49 | #include <arch/debug/print.h> |
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3529 | pillai | 50 | #include <genarch/fb/fb.h> |
51 | #include <genarch/fb/visuals.h> |
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3528 | pillai | 52 | |
53 | /* Addresses of devices. */ |
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4634 | pillai | 54 | #define QEMU_ICP_UART 0x16000000 |
3528 | pillai | 55 | #define QEMU_ICP_KBD 0x18000000 |
4628 | pillai | 56 | #define ICP_KBD_STAT 0x04 |
57 | #define ICP_KBD_DATA 0x08 |
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58 | #define ICP_KBD_INTR_STAT 0x10 |
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3528 | pillai | 59 | #define QEMU_ICP_RTC 0x13000000 |
4612 | pillai | 60 | #define QEMU_ICP_RTC1_LOAD_OFFSET 0x100 |
61 | #define QEMU_ICP_RTC1_READ_OFFSET 0x104 |
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62 | #define QEMU_ICP_RTC1_CTL_OFFSET 0x108 |
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63 | #define QEMU_ICP_RTC1_INTRCLR_OFFSET 0x10C |
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64 | #define QEMU_ICP_RTC1_BGLOAD_OFFSET 0x118 |
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65 | #define QEMU_ICP_RTC_CTL_VALUE 0x00E2 |
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3528 | pillai | 66 | #define QEMU_ICP_IRQC 0x14000000 |
3759 | pillai | 67 | #define QEMU_ICP_IRQC_MASK_OFFSET 0xC |
68 | #define QEMU_ICP_IRQC_UNMASK_OFFSET 0x8 |
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4634 | pillai | 69 | #define QEMU_ICP_FB 0x00800000 |
70 | #define QEMU_ICP_FB_FRAME (QEMU_ICP_FB >> 12) |
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71 | #define QEMU_ICP_FB_NUM_FRAME 300 |
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3528 | pillai | 72 | #define ICP_VGA 0xC0000000 |
73 | #define ICP_CMCR 0x10000000 |
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4634 | pillai | 74 | #define QEMU_ICP_SDRAM_MASK 0x1C |
75 | #define QEMU_ICP_SDRAMCR_OFFSET 0x20 |
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3528 | pillai | 76 | |
77 | /* IRQs */ |
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4612 | pillai | 78 | #define QEMU_ICP_KBD_IRQ 3 |
79 | #define QEMU_ICP_TIMER_IRQ 6 |
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3528 | pillai | 80 | |
4634 | pillai | 81 | #define SDRAM_SIZE (sdram[((*(uint32_t *)(ICP_CMCR+QEMU_ICP_SDRAMCR_OFFSET) & QEMU_ICP_SDRAM_MASK) >> 2)]) |
82 | |||
3528 | pillai | 83 | static qemu_icp_hw_map_t qemu_icp_hw_map; |
84 | static irq_t qemu_icp_timer_irq; |
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85 | |||
86 | static bool hw_map_init_called = false; |
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87 | static bool vga_init = false; |
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4634 | pillai | 88 | uint32_t sdram[8] = { |
89 | 16777216, /* 16mb */ |
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90 | 33554432, /* 32mb */ |
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91 | 67108864, /* 64mb */ |
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92 | 134217728, /* 128mb */ |
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93 | 268435456, /* 256mb */ |
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94 | 0, /* Reserverd */ |
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95 | 0, /* Reserverd */ |
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96 | |||
97 | }; |
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3528 | pillai | 98 | |
99 | void icp_vga_init(void); |
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100 | |||
101 | /** Initializes the vga |
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102 | * |
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103 | */ |
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104 | void icp_vga_init(void) |
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105 | { |
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106 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x14) = 0xA05F0000; |
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107 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x1C) = 0x12C11000; |
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108 | *(uint32_t*)qemu_icp_hw_map.vga = 0x3F1F3F9C; |
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109 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x4) = 0x080B61DF; |
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110 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x8) = 0x067F3800; |
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111 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x10) = QEMU_ICP_FB; |
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112 | *(uint32_t *)((char *)(qemu_icp_hw_map.vga) + 0x1C) = 0x182B; |
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113 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0xC) = 0x33805000; |
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114 | |||
115 | } |
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116 | |||
117 | /** Returns the mask of active interrupts. */ |
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118 | static inline uint32_t qemu_icp_irqc_get_sources(void) |
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119 | { |
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120 | return *((uint32_t *) qemu_icp_hw_map.irqc); |
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121 | } |
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122 | |||
123 | |||
124 | /** Masks interrupt. |
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125 | * |
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126 | * @param irq interrupt number |
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127 | */ |
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128 | static inline void qemu_icp_irqc_mask(uint32_t irq) |
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129 | { |
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4612 | pillai | 130 | *((uint32_t *) qemu_icp_hw_map.irqc_mask) = (1 << irq); |
3528 | pillai | 131 | } |
132 | |||
133 | |||
134 | /** Unmasks interrupt. |
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135 | * |
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136 | * @param irq interrupt number |
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137 | */ |
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138 | static inline void qemu_icp_irqc_unmask(uint32_t irq) |
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139 | { |
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4612 | pillai | 140 | *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= (1 << irq); |
3528 | pillai | 141 | } |
142 | |||
3529 | pillai | 143 | /** Initializes the icp frame buffer */ |
144 | void qemu_icp_fb_init(void) |
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145 | { |
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146 | fb_init(qemu_icp_get_fb_address(), 640, 480, 2560, VISUAL_BGR_8_8_8_0); |
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147 | } |
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3528 | pillai | 148 | |
149 | /** Initializes #qemu_icp_hw_map. */ |
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150 | void qemu_icp_hw_map_init(void) |
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151 | { |
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4634 | pillai | 152 | qemu_icp_hw_map.uart = hw_map(QEMU_ICP_UART, PAGE_SIZE); |
4628 | pillai | 153 | qemu_icp_hw_map.kbd_ctrl = hw_map(QEMU_ICP_KBD, PAGE_SIZE); |
154 | qemu_icp_hw_map.kbd_stat = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_STAT; |
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155 | qemu_icp_hw_map.kbd_data = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_DATA; |
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156 | qemu_icp_hw_map.kbd_intstat = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_INTR_STAT; |
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3528 | pillai | 157 | qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE); |
4612 | pillai | 158 | qemu_icp_hw_map.rtc1_load = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_LOAD_OFFSET; |
159 | qemu_icp_hw_map.rtc1_read = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_READ_OFFSET; |
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160 | qemu_icp_hw_map.rtc1_ctl = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_CTL_OFFSET; |
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161 | qemu_icp_hw_map.rtc1_intrclr = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_INTRCLR_OFFSET; |
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162 | qemu_icp_hw_map.rtc1_bgload = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_BGLOAD_OFFSET; |
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163 | |||
3528 | pillai | 164 | qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE); |
165 | qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET; |
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4634 | pillai | 166 | qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_UNMASK_OFFSET; |
3528 | pillai | 167 | qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE); |
4634 | pillai | 168 | qemu_icp_hw_map.sdramcr = qemu_icp_hw_map.cmcr + QEMU_ICP_SDRAMCR_OFFSET; |
3528 | pillai | 169 | qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE); |
170 | |||
171 | hw_map_init_called = true; |
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172 | } |
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173 | |||
174 | |||
175 | /** Acquire console back for kernel. */ |
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176 | void qemu_icp_grab_console(void) |
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177 | { |
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4629 | pillai | 178 | pl050_grab(); |
3528 | pillai | 179 | } |
180 | |||
181 | /** Return console to userspace. */ |
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182 | void qemu_icp_release_console(void) |
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183 | { |
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4629 | pillai | 184 | pl050_release(); |
3528 | pillai | 185 | } |
186 | |||
187 | /** Initializes console object representing qemu_icp console. |
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188 | * |
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189 | * @param devno device number. |
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190 | */ |
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191 | void qemu_icp_console_init(devno_t devno) |
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192 | { |
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193 | |||
4628 | pillai | 194 | qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ); |
4629 | pillai | 195 | pl050_init(devno, QEMU_ICP_KBD_IRQ, QEMU_ICP_KBD, qemu_icp_hw_map.kbd_ctrl); |
3528 | pillai | 196 | qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ); |
197 | } |
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198 | |||
199 | /** Starts qemu_icp Real Time Clock device, which asserts regular interrupts. |
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200 | * |
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201 | * @param frequency Interrupts frequency (0 disables RTC). |
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202 | */ |
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203 | static void qemu_icp_timer_start(uint32_t frequency) |
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204 | { |
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4615 | pillai | 205 | qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ); |
4612 | pillai | 206 | *((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency; |
207 | *((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency; |
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208 | *((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE; |
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209 | qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ); |
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3528 | pillai | 210 | } |
211 | |||
212 | static irq_ownership_t qemu_icp_timer_claim(void) |
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213 | { |
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214 | return IRQ_ACCEPT; |
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215 | } |
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216 | |||
217 | /** Timer interrupt handler. |
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218 | * |
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219 | * @param irq Interrupt information. |
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220 | * @param arg Not used. |
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221 | */ |
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222 | static void qemu_icp_timer_irq_handler(irq_t *irq, void *arg, ...) |
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223 | { |
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224 | /* |
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225 | * We are holding a lock which prevents preemption. |
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226 | * Release the lock, call clock() and reacquire the lock again. |
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227 | */ |
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4632 | pillai | 228 | |
4628 | pillai | 229 | *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 1; |
3528 | pillai | 230 | spinlock_unlock(&irq->lock); |
231 | clock(); |
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232 | spinlock_lock(&irq->lock); |
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233 | |||
234 | } |
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235 | |||
236 | /** Initializes and registers timer interrupt handler. */ |
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237 | static void qemu_icp_timer_irq_init(void) |
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238 | { |
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239 | irq_initialize(&qemu_icp_timer_irq); |
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240 | qemu_icp_timer_irq.devno = device_assign_devno(); |
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241 | qemu_icp_timer_irq.inr = QEMU_ICP_TIMER_IRQ; |
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242 | qemu_icp_timer_irq.claim = qemu_icp_timer_claim; |
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243 | qemu_icp_timer_irq.handler = qemu_icp_timer_irq_handler; |
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244 | |||
245 | irq_register(&qemu_icp_timer_irq); |
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246 | } |
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247 | |||
248 | |||
249 | /** Starts timer. |
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250 | * |
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251 | * Initiates regular timer interrupts after initializing |
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252 | * corresponding interrupt handler. |
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253 | */ |
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254 | void qemu_icp_timer_irq_start(void) |
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255 | { |
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256 | qemu_icp_timer_irq_init(); |
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257 | qemu_icp_timer_start(QEMU_ICP_TIMER_FREQ); |
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258 | } |
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259 | |||
260 | /** Returns the size of emulated memory. |
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261 | * |
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262 | * @return Size in bytes. |
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263 | */ |
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264 | size_t qemu_icp_get_memory_size(void) |
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265 | { |
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4634 | pillai | 266 | if (hw_map_init_called) { |
267 | return (sdram[((*(uint32_t *)qemu_icp_hw_map.sdramcr & QEMU_ICP_SDRAM_MASK) >> 2)]); |
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268 | } else { |
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269 | return SDRAM_SIZE; |
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270 | } |
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271 | |||
3528 | pillai | 272 | } |
273 | |||
274 | /** Prints a character. |
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275 | * |
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276 | * @param ch Character to be printed. |
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277 | */ |
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278 | void qemu_icp_debug_putc(char ch) |
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279 | { |
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280 | char *addr = 0; |
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281 | if (!hw_map_init_called) { |
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282 | addr = (char *) QEMU_ICP_KBD; |
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283 | } else { |
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4634 | pillai | 284 | addr = (char *) qemu_icp_hw_map.uart; |
3528 | pillai | 285 | } |
286 | |||
287 | if (ch == '\n') |
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288 | *(addr) = '\r'; |
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289 | *(addr) = ch; |
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290 | } |
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291 | |||
292 | /** Stops qemu_icp. */ |
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293 | void qemu_icp_cpu_halt(void) |
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294 | { |
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4628 | pillai | 295 | while (1); |
3528 | pillai | 296 | } |
297 | |||
4634 | pillai | 298 | /** interrupt exception handler. |
3528 | pillai | 299 | * |
300 | * Determines sources of the interrupt from interrupt controller and |
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301 | * calls high-level handlers for them. |
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302 | * |
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303 | * @param exc_no Interrupt exception number. |
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304 | * @param istate Saved processor state. |
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305 | */ |
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306 | void qemu_icp_irq_exception(int exc_no, istate_t *istate) |
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307 | { |
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308 | uint32_t sources = qemu_icp_irqc_get_sources(); |
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309 | int i; |
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310 | |||
311 | for (i = 0; i < QEMU_ICP_IRQC_MAX_IRQ; i++) { |
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312 | if (sources & (1 << i)) { |
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313 | irq_t *irq = irq_dispatch_and_lock(i); |
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314 | if (irq) { |
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315 | /* The IRQ handler was found. */ |
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316 | irq->handler(irq, irq->arg); |
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317 | spinlock_unlock(&irq->lock); |
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318 | } else { |
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319 | /* Spurious interrupt.*/ |
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320 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", |
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321 | CPU->id, i); |
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322 | } |
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323 | } |
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324 | } |
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325 | } |
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326 | |||
327 | /** Returns address of framebuffer device. |
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328 | * |
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329 | * @return Address of framebuffer device. |
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330 | */ |
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331 | uintptr_t qemu_icp_get_fb_address(void) |
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332 | { |
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333 | if (!vga_init) { |
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334 | icp_vga_init(); |
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335 | vga_init = true; |
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336 | } |
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337 | return (uintptr_t) QEMU_ICP_FB; |
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338 | } |
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339 | |||
4634 | pillai | 340 | /* |
341 | * Integrator specific frame initialization |
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342 | */ |
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343 | void |
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344 | qemu_icp_frame_init(void) |
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345 | { |
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346 | frame_mark_unavailable(QEMU_ICP_FB_FRAME, QEMU_ICP_FB_NUM_FRAME); |
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347 | } |
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3528 | pillai | 348 | |
4634 | pillai | 349 | |
3528 | pillai | 350 | /** @} |
351 | */ |