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3528 | pillai | 1 | /* |
4629 | pillai | 2 | * Copyright (c) 2009 Vineeth Pillai |
3528 | pillai | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32qemu_icp |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | * @brief QEMU icp drivers. |
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34 | */ |
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35 | |||
36 | #include <interrupt.h> |
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37 | #include <ipc/irq.h> |
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38 | #include <console/chardev.h> |
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39 | #include <arch/drivers/qemu.h> |
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4629 | pillai | 40 | #include <arch/drivers/pl050.h> |
3528 | pillai | 41 | #include <console/console.h> |
42 | #include <sysinfo/sysinfo.h> |
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43 | #include <print.h> |
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44 | #include <ddi/device.h> |
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45 | #include <mm/page.h> |
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46 | #include <arch/machine.h> |
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47 | #include <arch/debug/print.h> |
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3529 | pillai | 48 | #include <genarch/fb/fb.h> |
49 | #include <genarch/fb/visuals.h> |
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3528 | pillai | 50 | |
51 | /* Addresses of devices. */ |
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52 | #define QEMU_ICP_VIDEORAM 0x16000000 |
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53 | #define QEMU_ICP_KBD 0x18000000 |
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4628 | pillai | 54 | #define ICP_KBD_STAT 0x04 |
55 | #define ICP_KBD_DATA 0x08 |
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56 | #define ICP_KBD_INTR_STAT 0x10 |
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3528 | pillai | 57 | #define QEMU_ICP_HALT_OFFSET 0x10 |
58 | #define QEMU_ICP_RTC 0x13000000 |
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4612 | pillai | 59 | #define QEMU_ICP_RTC1_LOAD_OFFSET 0x100 |
60 | #define QEMU_ICP_RTC1_READ_OFFSET 0x104 |
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61 | #define QEMU_ICP_RTC1_CTL_OFFSET 0x108 |
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62 | #define QEMU_ICP_RTC1_INTRCLR_OFFSET 0x10C |
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63 | #define QEMU_ICP_RTC1_BGLOAD_OFFSET 0x118 |
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64 | #define QEMU_ICP_RTC_CTL_VALUE 0x00E2 |
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3528 | pillai | 65 | #define QEMU_ICP_IRQC 0x14000000 |
3759 | pillai | 66 | #define QEMU_ICP_IRQC_MASK_OFFSET 0xC |
67 | #define QEMU_ICP_IRQC_UNMASK_OFFSET 0x8 |
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3528 | pillai | 68 | #define QEMU_ICP_MP 0x11000000 |
69 | #define QEMU_ICP_MP_MEMSIZE_OFFSET 0x0090 |
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4628 | pillai | 70 | #define QEMU_ICP_FB 0x01000000 |
3528 | pillai | 71 | |
72 | #define ICP_VGA 0xC0000000 |
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73 | #define ICP_CMCR 0x10000000 |
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74 | |||
75 | /* IRQs */ |
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4612 | pillai | 76 | #define QEMU_ICP_KBD_IRQ 3 |
77 | #define QEMU_ICP_TIMER_IRQ 6 |
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3528 | pillai | 78 | |
79 | static qemu_icp_hw_map_t qemu_icp_hw_map; |
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80 | static irq_t qemu_icp_timer_irq; |
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81 | |||
82 | static bool hw_map_init_called = false; |
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83 | static bool vga_init = false; |
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84 | |||
85 | void icp_vga_init(void); |
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86 | |||
87 | /** Initializes the vga |
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88 | * |
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89 | */ |
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90 | void icp_vga_init(void) |
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91 | { |
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92 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x14) = 0xA05F0000; |
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93 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x1C) = 0x12C11000; |
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94 | *(uint32_t*)qemu_icp_hw_map.vga = 0x3F1F3F9C; |
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95 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x4) = 0x080B61DF; |
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96 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x8) = 0x067F3800; |
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97 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x10) = QEMU_ICP_FB; |
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98 | *(uint32_t *)((char *)(qemu_icp_hw_map.vga) + 0x1C) = 0x182B; |
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99 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0xC) = 0x33805000; |
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100 | |||
101 | } |
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102 | |||
103 | /** Returns the mask of active interrupts. */ |
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104 | static inline uint32_t qemu_icp_irqc_get_sources(void) |
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105 | { |
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106 | return *((uint32_t *) qemu_icp_hw_map.irqc); |
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107 | } |
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108 | |||
109 | |||
110 | /** Masks interrupt. |
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111 | * |
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112 | * @param irq interrupt number |
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113 | */ |
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114 | static inline void qemu_icp_irqc_mask(uint32_t irq) |
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115 | { |
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4612 | pillai | 116 | *((uint32_t *) qemu_icp_hw_map.irqc_mask) = (1 << irq); |
3528 | pillai | 117 | } |
118 | |||
119 | |||
120 | /** Unmasks interrupt. |
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121 | * |
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122 | * @param irq interrupt number |
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123 | */ |
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124 | static inline void qemu_icp_irqc_unmask(uint32_t irq) |
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125 | { |
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4612 | pillai | 126 | *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= (1 << irq); |
3528 | pillai | 127 | } |
128 | |||
3529 | pillai | 129 | /** Initializes the icp frame buffer */ |
130 | void qemu_icp_fb_init(void) |
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131 | { |
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132 | fb_init(qemu_icp_get_fb_address(), 640, 480, 2560, VISUAL_BGR_8_8_8_0); |
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133 | } |
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3528 | pillai | 134 | |
135 | /** Initializes #qemu_icp_hw_map. */ |
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136 | void qemu_icp_hw_map_init(void) |
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137 | { |
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138 | qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE); |
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4628 | pillai | 139 | qemu_icp_hw_map.kbd_ctrl = hw_map(QEMU_ICP_KBD, PAGE_SIZE); |
140 | qemu_icp_hw_map.kbd_stat = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_STAT; |
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141 | qemu_icp_hw_map.kbd_data = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_DATA; |
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142 | qemu_icp_hw_map.kbd_intstat = qemu_icp_hw_map.kbd_ctrl + ICP_KBD_INTR_STAT; |
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3528 | pillai | 143 | qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE); |
4612 | pillai | 144 | qemu_icp_hw_map.rtc1_load = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_LOAD_OFFSET; |
145 | qemu_icp_hw_map.rtc1_read = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_READ_OFFSET; |
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146 | qemu_icp_hw_map.rtc1_ctl = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_CTL_OFFSET; |
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147 | qemu_icp_hw_map.rtc1_intrclr = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_INTRCLR_OFFSET; |
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148 | qemu_icp_hw_map.rtc1_bgload = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_BGLOAD_OFFSET; |
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149 | |||
3528 | pillai | 150 | qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE); |
151 | qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET; |
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152 | qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc + |
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153 | QEMU_ICP_IRQC_UNMASK_OFFSET; |
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154 | qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE); |
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155 | qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE); |
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156 | |||
157 | //icp_vga_init(); |
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158 | |||
159 | hw_map_init_called = true; |
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160 | } |
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161 | |||
162 | |||
163 | /** Acquire console back for kernel. */ |
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164 | void qemu_icp_grab_console(void) |
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165 | { |
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4629 | pillai | 166 | pl050_grab(); |
3528 | pillai | 167 | } |
168 | |||
169 | /** Return console to userspace. */ |
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170 | void qemu_icp_release_console(void) |
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171 | { |
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4629 | pillai | 172 | pl050_release(); |
3528 | pillai | 173 | } |
174 | |||
175 | /** Initializes console object representing qemu_icp console. |
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176 | * |
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177 | * @param devno device number. |
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178 | */ |
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179 | void qemu_icp_console_init(devno_t devno) |
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180 | { |
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181 | |||
4628 | pillai | 182 | qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ); |
4629 | pillai | 183 | pl050_init(devno, QEMU_ICP_KBD_IRQ, QEMU_ICP_KBD, qemu_icp_hw_map.kbd_ctrl); |
3528 | pillai | 184 | qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ); |
185 | } |
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186 | |||
187 | /** Starts qemu_icp Real Time Clock device, which asserts regular interrupts. |
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188 | * |
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189 | * @param frequency Interrupts frequency (0 disables RTC). |
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190 | */ |
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191 | static void qemu_icp_timer_start(uint32_t frequency) |
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192 | { |
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4615 | pillai | 193 | qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ); |
4612 | pillai | 194 | *((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency; |
195 | *((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency; |
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196 | *((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE; |
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197 | qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ); |
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3528 | pillai | 198 | } |
199 | |||
200 | static irq_ownership_t qemu_icp_timer_claim(void) |
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201 | { |
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202 | return IRQ_ACCEPT; |
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203 | } |
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204 | |||
205 | /** Timer interrupt handler. |
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206 | * |
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207 | * @param irq Interrupt information. |
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208 | * @param arg Not used. |
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209 | */ |
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210 | static void qemu_icp_timer_irq_handler(irq_t *irq, void *arg, ...) |
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211 | { |
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212 | /* |
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213 | * We are holding a lock which prevents preemption. |
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214 | * Release the lock, call clock() and reacquire the lock again. |
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215 | */ |
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4628 | pillai | 216 | *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 1; |
3528 | pillai | 217 | spinlock_unlock(&irq->lock); |
218 | clock(); |
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219 | spinlock_lock(&irq->lock); |
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220 | |||
221 | } |
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222 | |||
223 | /** Initializes and registers timer interrupt handler. */ |
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224 | static void qemu_icp_timer_irq_init(void) |
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225 | { |
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226 | irq_initialize(&qemu_icp_timer_irq); |
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227 | qemu_icp_timer_irq.devno = device_assign_devno(); |
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228 | qemu_icp_timer_irq.inr = QEMU_ICP_TIMER_IRQ; |
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229 | qemu_icp_timer_irq.claim = qemu_icp_timer_claim; |
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230 | qemu_icp_timer_irq.handler = qemu_icp_timer_irq_handler; |
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231 | |||
232 | irq_register(&qemu_icp_timer_irq); |
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233 | } |
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234 | |||
235 | |||
236 | /** Starts timer. |
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237 | * |
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238 | * Initiates regular timer interrupts after initializing |
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239 | * corresponding interrupt handler. |
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240 | */ |
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241 | void qemu_icp_timer_irq_start(void) |
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242 | { |
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243 | qemu_icp_timer_irq_init(); |
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244 | qemu_icp_timer_start(QEMU_ICP_TIMER_FREQ); |
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245 | } |
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246 | |||
247 | /** Returns the size of emulated memory. |
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248 | * |
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249 | * @return Size in bytes. |
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250 | */ |
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251 | size_t qemu_icp_get_memory_size(void) |
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252 | { |
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253 | //return *((int *) (QEMU_ICP_MP + QEMU_ICP_MP_MEMSIZE_OFFSET)); |
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254 | return 0x2000000; |
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255 | } |
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256 | |||
257 | /** Prints a character. |
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258 | * |
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259 | * @param ch Character to be printed. |
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260 | */ |
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261 | void qemu_icp_debug_putc(char ch) |
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262 | { |
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263 | char *addr = 0; |
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264 | if (!hw_map_init_called) { |
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265 | addr = (char *) QEMU_ICP_KBD; |
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266 | } else { |
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267 | addr = (char *) qemu_icp_hw_map.videoram; |
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268 | } |
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269 | |||
270 | if (ch == '\n') |
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271 | *(addr) = '\r'; |
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272 | *(addr) = ch; |
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273 | } |
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274 | |||
275 | /** Stops qemu_icp. */ |
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276 | void qemu_icp_cpu_halt(void) |
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277 | { |
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4628 | pillai | 278 | while (1); |
3528 | pillai | 279 | } |
280 | |||
281 | /** Gxemul specific interrupt exception handler. |
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282 | * |
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283 | * Determines sources of the interrupt from interrupt controller and |
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284 | * calls high-level handlers for them. |
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285 | * |
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286 | * @param exc_no Interrupt exception number. |
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287 | * @param istate Saved processor state. |
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288 | */ |
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289 | void qemu_icp_irq_exception(int exc_no, istate_t *istate) |
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290 | { |
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291 | uint32_t sources = qemu_icp_irqc_get_sources(); |
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292 | int i; |
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293 | |||
294 | for (i = 0; i < QEMU_ICP_IRQC_MAX_IRQ; i++) { |
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295 | if (sources & (1 << i)) { |
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296 | irq_t *irq = irq_dispatch_and_lock(i); |
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297 | if (irq) { |
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298 | /* The IRQ handler was found. */ |
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299 | irq->handler(irq, irq->arg); |
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300 | spinlock_unlock(&irq->lock); |
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301 | } else { |
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302 | /* Spurious interrupt.*/ |
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303 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", |
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304 | CPU->id, i); |
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305 | } |
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306 | } |
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307 | } |
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308 | } |
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309 | |||
310 | /** Returns address of framebuffer device. |
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311 | * |
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312 | * @return Address of framebuffer device. |
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313 | */ |
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314 | uintptr_t qemu_icp_get_fb_address(void) |
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315 | { |
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316 | if (!vga_init) { |
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317 | icp_vga_init(); |
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318 | vga_init = true; |
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319 | } |
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320 | return (uintptr_t) QEMU_ICP_FB; |
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321 | } |
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322 | |||
323 | |||
324 | /** @} |
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325 | */ |