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Rev | Author | Line No. | Line |
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3528 | pillai | 1 | /* |
2 | * Copyright (c) 2007 Michal Kebrt, Petr Stepan |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32qemu_icp |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | * @brief QEMU icp drivers. |
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34 | */ |
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35 | |||
36 | #include <interrupt.h> |
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37 | #include <ipc/irq.h> |
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38 | #include <console/chardev.h> |
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39 | #include <arch/drivers/qemu.h> |
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40 | #include <console/console.h> |
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41 | #include <sysinfo/sysinfo.h> |
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42 | #include <print.h> |
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43 | #include <ddi/device.h> |
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44 | #include <mm/page.h> |
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45 | #include <arch/machine.h> |
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46 | #include <arch/debug/print.h> |
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3529 | pillai | 47 | #include <genarch/fb/fb.h> |
48 | #include <genarch/fb/visuals.h> |
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3528 | pillai | 49 | |
50 | /* Addresses of devices. */ |
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51 | #define QEMU_ICP_VIDEORAM 0x16000000 |
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52 | #define QEMU_ICP_KBD 0x18000000 |
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53 | #define QEMU_ICP_HALT_OFFSET 0x10 |
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54 | #define QEMU_ICP_RTC 0x13000000 |
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4612 | pillai | 55 | #define QEMU_ICP_RTC1_LOAD_OFFSET 0x100 |
56 | #define QEMU_ICP_RTC1_READ_OFFSET 0x104 |
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57 | #define QEMU_ICP_RTC1_CTL_OFFSET 0x108 |
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58 | #define QEMU_ICP_RTC1_INTRCLR_OFFSET 0x10C |
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59 | #define QEMU_ICP_RTC1_BGLOAD_OFFSET 0x118 |
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60 | #define QEMU_ICP_RTC_CTL_VALUE 0x00E2 |
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3528 | pillai | 61 | #define QEMU_ICP_IRQC 0x14000000 |
3759 | pillai | 62 | #define QEMU_ICP_IRQC_MASK_OFFSET 0xC |
63 | #define QEMU_ICP_IRQC_UNMASK_OFFSET 0x8 |
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3528 | pillai | 64 | #define QEMU_ICP_MP 0x11000000 |
65 | #define QEMU_ICP_MP_MEMSIZE_OFFSET 0x0090 |
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66 | #define QEMU_ICP_FB 0x94000 |
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67 | |||
68 | #define ICP_VGA 0xC0000000 |
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69 | #define ICP_CMCR 0x10000000 |
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70 | |||
71 | /* IRQs */ |
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4612 | pillai | 72 | #define QEMU_ICP_KBD_IRQ 3 |
73 | #define QEMU_ICP_TIMER_IRQ 6 |
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3528 | pillai | 74 | |
75 | static qemu_icp_hw_map_t qemu_icp_hw_map; |
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76 | static chardev_t console; |
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77 | static irq_t qemu_icp_console_irq; |
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78 | static irq_t qemu_icp_timer_irq; |
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79 | |||
80 | static bool hw_map_init_called = false; |
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81 | static bool vga_init = false; |
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82 | |||
83 | static void qemu_icp_kbd_enable(chardev_t *dev); |
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84 | static void qemu_icp_kbd_disable(chardev_t *dev); |
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85 | static void qemu_icp_write(chardev_t *dev, const char ch); |
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86 | static char qemu_icp_do_read(chardev_t *dev); |
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87 | void icp_vga_init(void); |
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88 | |||
89 | static chardev_operations_t qemu_icp_ops = { |
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90 | .resume = qemu_icp_kbd_enable, |
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91 | .suspend = qemu_icp_kbd_disable, |
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92 | .write = qemu_icp_write, |
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93 | .read = qemu_icp_do_read, |
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94 | }; |
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95 | |||
96 | /** Initializes the vga |
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97 | * |
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98 | */ |
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99 | void icp_vga_init(void) |
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100 | { |
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101 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x14) = 0xA05F0000; |
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102 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x1C) = 0x12C11000; |
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103 | *(uint32_t*)qemu_icp_hw_map.vga = 0x3F1F3F9C; |
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104 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x4) = 0x080B61DF; |
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105 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x8) = 0x067F3800; |
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106 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x10) = QEMU_ICP_FB; |
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107 | *(uint32_t *)((char *)(qemu_icp_hw_map.vga) + 0x1C) = 0x182B; |
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108 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0xC) = 0x33805000; |
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109 | |||
110 | } |
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111 | |||
112 | /** Returns the mask of active interrupts. */ |
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113 | static inline uint32_t qemu_icp_irqc_get_sources(void) |
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114 | { |
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115 | return *((uint32_t *) qemu_icp_hw_map.irqc); |
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116 | } |
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117 | |||
118 | |||
119 | /** Masks interrupt. |
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120 | * |
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121 | * @param irq interrupt number |
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122 | */ |
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123 | static inline void qemu_icp_irqc_mask(uint32_t irq) |
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124 | { |
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4612 | pillai | 125 | *((uint32_t *) qemu_icp_hw_map.irqc_mask) = (1 << irq); |
3528 | pillai | 126 | } |
127 | |||
128 | |||
129 | /** Unmasks interrupt. |
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130 | * |
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131 | * @param irq interrupt number |
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132 | */ |
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133 | static inline void qemu_icp_irqc_unmask(uint32_t irq) |
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134 | { |
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4612 | pillai | 135 | *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= (1 << irq); |
3528 | pillai | 136 | } |
137 | |||
3529 | pillai | 138 | /** Initializes the icp frame buffer */ |
139 | void qemu_icp_fb_init(void) |
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140 | { |
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141 | fb_init(qemu_icp_get_fb_address(), 640, 480, 2560, VISUAL_BGR_8_8_8_0); |
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142 | } |
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3528 | pillai | 143 | |
144 | /** Initializes #qemu_icp_hw_map. */ |
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145 | void qemu_icp_hw_map_init(void) |
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146 | { |
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147 | qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE); |
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148 | qemu_icp_hw_map.kbd = hw_map(QEMU_ICP_KBD, PAGE_SIZE); |
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149 | qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE); |
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4612 | pillai | 150 | qemu_icp_hw_map.rtc1_load = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_LOAD_OFFSET; |
151 | qemu_icp_hw_map.rtc1_read = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_READ_OFFSET; |
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152 | qemu_icp_hw_map.rtc1_ctl = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_CTL_OFFSET; |
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153 | qemu_icp_hw_map.rtc1_intrclr = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_INTRCLR_OFFSET; |
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154 | qemu_icp_hw_map.rtc1_bgload = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_BGLOAD_OFFSET; |
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155 | |||
3528 | pillai | 156 | qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE); |
157 | qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET; |
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158 | qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc + |
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159 | QEMU_ICP_IRQC_UNMASK_OFFSET; |
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160 | qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE); |
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161 | qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE); |
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162 | |||
163 | //icp_vga_init(); |
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164 | |||
165 | hw_map_init_called = true; |
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166 | } |
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167 | |||
168 | |||
169 | /** Putchar that works with qemu_icp. |
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170 | * |
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171 | * @param dev Not used. |
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172 | * @param ch Characted to be printed. |
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173 | */ |
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174 | static void qemu_icp_write(chardev_t *dev, const char ch) |
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175 | { |
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176 | *((char *) qemu_icp_hw_map.videoram) = ch; |
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177 | } |
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178 | |||
179 | /** Enables qemu_icp keyboard (interrupt unmasked). |
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180 | * |
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181 | * @param dev Not used. |
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182 | * |
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183 | * Called from getc(). |
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184 | */ |
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185 | static void qemu_icp_kbd_enable(chardev_t *dev) |
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186 | { |
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187 | qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ); |
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188 | } |
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189 | |||
190 | /** Disables qemu_icp keyboard (interrupt masked). |
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191 | * |
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192 | * @param dev not used |
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193 | * |
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194 | * Called from getc(). |
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195 | */ |
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196 | static void qemu_icp_kbd_disable(chardev_t *dev) |
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197 | { |
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198 | qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ); |
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199 | } |
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200 | |||
201 | /** Read character using polling, assume interrupts disabled. |
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202 | * |
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203 | * @param dev Not used. |
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204 | */ |
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205 | static char qemu_icp_do_read(chardev_t *dev) |
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206 | { |
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207 | char ch; |
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208 | |||
209 | while (1) { |
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210 | ch = *((volatile char *) qemu_icp_hw_map.kbd); |
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211 | if (ch) { |
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212 | if (ch == '\r') |
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213 | return '\n'; |
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214 | if (ch == 0x7f) |
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215 | return '\b'; |
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216 | return ch; |
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217 | } |
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218 | } |
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219 | } |
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220 | |||
221 | /** Process keyboard interrupt. |
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222 | * |
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223 | * @param irq IRQ information. |
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224 | * @param arg Not used. |
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225 | */ |
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226 | static void qemu_icp_irq_handler(irq_t *irq, void *arg, ...) |
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227 | { |
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228 | if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) { |
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229 | ipc_irq_send_notif(irq); |
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230 | } else { |
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231 | char ch = 0; |
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232 | |||
233 | ch = *((char *) qemu_icp_hw_map.kbd); |
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234 | if (ch == '\r') { |
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235 | ch = '\n'; |
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236 | } |
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237 | if (ch == 0x7f) { |
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238 | ch = '\b'; |
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239 | } |
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240 | chardev_push_character(&console, ch); |
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241 | } |
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242 | } |
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243 | |||
244 | static irq_ownership_t qemu_icp_claim(void) |
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245 | { |
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246 | return IRQ_ACCEPT; |
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247 | } |
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248 | |||
249 | |||
250 | /** Acquire console back for kernel. */ |
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251 | void qemu_icp_grab_console(void) |
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252 | { |
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253 | ipl_t ipl = interrupts_disable(); |
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254 | spinlock_lock(&qemu_icp_console_irq.lock); |
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255 | qemu_icp_console_irq.notif_cfg.notify = false; |
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256 | spinlock_unlock(&qemu_icp_console_irq.lock); |
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257 | interrupts_restore(ipl); |
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258 | } |
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259 | |||
260 | /** Return console to userspace. */ |
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261 | void qemu_icp_release_console(void) |
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262 | { |
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263 | ipl_t ipl = interrupts_disable(); |
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264 | spinlock_lock(&qemu_icp_console_irq.lock); |
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265 | if (qemu_icp_console_irq.notif_cfg.answerbox) { |
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266 | qemu_icp_console_irq.notif_cfg.notify = true; |
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267 | } |
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268 | spinlock_unlock(&qemu_icp_console_irq.lock); |
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269 | interrupts_restore(ipl); |
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270 | } |
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271 | |||
272 | /** Initializes console object representing qemu_icp console. |
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273 | * |
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274 | * @param devno device number. |
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275 | */ |
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276 | void qemu_icp_console_init(devno_t devno) |
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277 | { |
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4615 | pillai | 278 | qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ); |
3528 | pillai | 279 | chardev_initialize("qemu_icp_console", &console, &qemu_icp_ops); |
280 | stdin = &console; |
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281 | stdout = &console; |
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282 | |||
283 | irq_initialize(&qemu_icp_console_irq); |
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284 | qemu_icp_console_irq.devno = devno; |
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285 | qemu_icp_console_irq.inr = QEMU_ICP_KBD_IRQ; |
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286 | qemu_icp_console_irq.claim = qemu_icp_claim; |
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287 | qemu_icp_console_irq.handler = qemu_icp_irq_handler; |
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288 | irq_register(&qemu_icp_console_irq); |
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289 | |||
290 | qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ); |
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291 | |||
292 | sysinfo_set_item_val("kbd", NULL, true); |
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293 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
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294 | sysinfo_set_item_val("kbd.inr", NULL, QEMU_ICP_KBD_IRQ); |
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295 | sysinfo_set_item_val("kbd.address.virtual", NULL, qemu_icp_hw_map.kbd); |
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296 | } |
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297 | |||
298 | /** Starts qemu_icp Real Time Clock device, which asserts regular interrupts. |
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299 | * |
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300 | * @param frequency Interrupts frequency (0 disables RTC). |
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301 | */ |
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302 | static void qemu_icp_timer_start(uint32_t frequency) |
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303 | { |
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4615 | pillai | 304 | qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ); |
4612 | pillai | 305 | *((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency; |
306 | *((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency; |
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307 | *((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE; |
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308 | qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ); |
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3528 | pillai | 309 | } |
310 | |||
311 | static irq_ownership_t qemu_icp_timer_claim(void) |
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312 | { |
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4615 | pillai | 313 | *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 1; |
3528 | pillai | 314 | return IRQ_ACCEPT; |
315 | } |
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316 | |||
317 | /** Timer interrupt handler. |
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318 | * |
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319 | * @param irq Interrupt information. |
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320 | * @param arg Not used. |
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321 | */ |
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322 | static void qemu_icp_timer_irq_handler(irq_t *irq, void *arg, ...) |
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323 | { |
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324 | /* |
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325 | * We are holding a lock which prevents preemption. |
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326 | * Release the lock, call clock() and reacquire the lock again. |
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327 | */ |
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328 | spinlock_unlock(&irq->lock); |
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329 | clock(); |
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330 | spinlock_lock(&irq->lock); |
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331 | |||
332 | } |
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333 | |||
334 | /** Initializes and registers timer interrupt handler. */ |
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335 | static void qemu_icp_timer_irq_init(void) |
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336 | { |
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337 | irq_initialize(&qemu_icp_timer_irq); |
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338 | qemu_icp_timer_irq.devno = device_assign_devno(); |
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339 | qemu_icp_timer_irq.inr = QEMU_ICP_TIMER_IRQ; |
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340 | qemu_icp_timer_irq.claim = qemu_icp_timer_claim; |
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341 | qemu_icp_timer_irq.handler = qemu_icp_timer_irq_handler; |
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342 | |||
343 | irq_register(&qemu_icp_timer_irq); |
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344 | } |
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345 | |||
346 | |||
347 | /** Starts timer. |
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348 | * |
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349 | * Initiates regular timer interrupts after initializing |
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350 | * corresponding interrupt handler. |
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351 | */ |
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352 | void qemu_icp_timer_irq_start(void) |
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353 | { |
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354 | qemu_icp_timer_irq_init(); |
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355 | qemu_icp_timer_start(QEMU_ICP_TIMER_FREQ); |
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356 | } |
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357 | |||
358 | /** Returns the size of emulated memory. |
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359 | * |
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360 | * @return Size in bytes. |
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361 | */ |
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362 | size_t qemu_icp_get_memory_size(void) |
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363 | { |
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364 | //return *((int *) (QEMU_ICP_MP + QEMU_ICP_MP_MEMSIZE_OFFSET)); |
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365 | return 0x2000000; |
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366 | } |
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367 | |||
368 | /** Prints a character. |
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369 | * |
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370 | * @param ch Character to be printed. |
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371 | */ |
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372 | void qemu_icp_debug_putc(char ch) |
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373 | { |
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374 | char *addr = 0; |
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375 | if (!hw_map_init_called) { |
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376 | addr = (char *) QEMU_ICP_KBD; |
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377 | } else { |
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378 | addr = (char *) qemu_icp_hw_map.videoram; |
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379 | } |
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380 | |||
381 | if (ch == '\n') |
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382 | *(addr) = '\r'; |
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383 | *(addr) = ch; |
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384 | } |
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385 | |||
386 | /** Stops qemu_icp. */ |
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387 | void qemu_icp_cpu_halt(void) |
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388 | { |
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389 | char * addr = 0; |
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390 | if (!hw_map_init_called) { |
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391 | addr = (char *) QEMU_ICP_KBD; |
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392 | } else { |
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393 | addr = (char *) qemu_icp_hw_map.videoram; |
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394 | } |
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395 | |||
396 | *(addr + QEMU_ICP_HALT_OFFSET) = '\0'; |
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397 | } |
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398 | |||
399 | /** Gxemul specific interrupt exception handler. |
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400 | * |
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401 | * Determines sources of the interrupt from interrupt controller and |
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402 | * calls high-level handlers for them. |
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403 | * |
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404 | * @param exc_no Interrupt exception number. |
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405 | * @param istate Saved processor state. |
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406 | */ |
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407 | void qemu_icp_irq_exception(int exc_no, istate_t *istate) |
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408 | { |
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409 | uint32_t sources = qemu_icp_irqc_get_sources(); |
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410 | int i; |
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411 | |||
412 | for (i = 0; i < QEMU_ICP_IRQC_MAX_IRQ; i++) { |
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413 | if (sources & (1 << i)) { |
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414 | irq_t *irq = irq_dispatch_and_lock(i); |
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415 | if (irq) { |
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416 | /* The IRQ handler was found. */ |
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417 | irq->handler(irq, irq->arg); |
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418 | spinlock_unlock(&irq->lock); |
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419 | } else { |
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420 | /* Spurious interrupt.*/ |
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421 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", |
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422 | CPU->id, i); |
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423 | } |
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424 | } |
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425 | } |
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426 | } |
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427 | |||
428 | /** Returns address of framebuffer device. |
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429 | * |
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430 | * @return Address of framebuffer device. |
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431 | */ |
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432 | uintptr_t qemu_icp_get_fb_address(void) |
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433 | { |
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434 | if (!vga_init) { |
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435 | icp_vga_init(); |
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436 | vga_init = true; |
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437 | } |
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438 | return (uintptr_t) QEMU_ICP_FB; |
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439 | } |
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440 | |||
441 | |||
442 | /** @} |
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443 | */ |