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Rev | Author | Line No. | Line |
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3528 | pillai | 1 | /* |
2 | * Copyright (c) 2007 Michal Kebrt, Petr Stepan |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32qemu_icp |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | * @brief QEMU icp drivers. |
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34 | */ |
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35 | |||
36 | #include <interrupt.h> |
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37 | #include <ipc/irq.h> |
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38 | #include <console/chardev.h> |
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39 | #include <arch/drivers/qemu.h> |
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40 | #include <console/console.h> |
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41 | #include <sysinfo/sysinfo.h> |
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42 | #include <print.h> |
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43 | #include <ddi/device.h> |
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44 | #include <mm/page.h> |
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45 | #include <arch/machine.h> |
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46 | #include <arch/debug/print.h> |
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3529 | pillai | 47 | #include <genarch/fb/fb.h> |
48 | #include <genarch/fb/visuals.h> |
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3528 | pillai | 49 | |
50 | /* Addresses of devices. */ |
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51 | #define QEMU_ICP_VIDEORAM 0x16000000 |
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52 | #define QEMU_ICP_KBD 0x18000000 |
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53 | #define QEMU_ICP_HALT_OFFSET 0x10 |
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54 | #define QEMU_ICP_RTC 0x13000000 |
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55 | #define QEMU_ICP_RTC_FREQ_OFFSET 0x100 |
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56 | #define QEMU_ICP_RTC_ACK_OFFSET 0x110 |
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57 | #define QEMU_ICP_IRQC 0x14000000 |
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3759 | pillai | 58 | #define QEMU_ICP_IRQC_MASK_OFFSET 0xC |
59 | #define QEMU_ICP_IRQC_UNMASK_OFFSET 0x8 |
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3528 | pillai | 60 | #define QEMU_ICP_MP 0x11000000 |
61 | #define QEMU_ICP_MP_MEMSIZE_OFFSET 0x0090 |
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62 | #define QEMU_ICP_FB 0x94000 |
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63 | |||
64 | #define ICP_VGA 0xC0000000 |
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65 | #define ICP_CMCR 0x10000000 |
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66 | |||
67 | /* IRQs */ |
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3759 | pillai | 68 | #define QEMU_ICP_KBD_IRQ 0x03 |
69 | #define QEMU_ICP_TIMER_IRQ 0x05 |
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3528 | pillai | 70 | |
71 | static qemu_icp_hw_map_t qemu_icp_hw_map; |
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72 | static chardev_t console; |
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73 | static irq_t qemu_icp_console_irq; |
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74 | static irq_t qemu_icp_timer_irq; |
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75 | |||
76 | static bool hw_map_init_called = false; |
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77 | static bool vga_init = false; |
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78 | |||
79 | static void qemu_icp_kbd_enable(chardev_t *dev); |
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80 | static void qemu_icp_kbd_disable(chardev_t *dev); |
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81 | static void qemu_icp_write(chardev_t *dev, const char ch); |
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82 | static char qemu_icp_do_read(chardev_t *dev); |
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83 | void icp_vga_init(void); |
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84 | |||
85 | static chardev_operations_t qemu_icp_ops = { |
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86 | .resume = qemu_icp_kbd_enable, |
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87 | .suspend = qemu_icp_kbd_disable, |
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88 | .write = qemu_icp_write, |
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89 | .read = qemu_icp_do_read, |
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90 | }; |
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91 | |||
92 | /** Initializes the vga |
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93 | * |
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94 | */ |
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95 | void icp_vga_init(void) |
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96 | { |
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97 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x14) = 0xA05F0000; |
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98 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x1C) = 0x12C11000; |
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99 | *(uint32_t*)qemu_icp_hw_map.vga = 0x3F1F3F9C; |
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100 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x4) = 0x080B61DF; |
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101 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x8) = 0x067F3800; |
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102 | *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x10) = QEMU_ICP_FB; |
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103 | *(uint32_t *)((char *)(qemu_icp_hw_map.vga) + 0x1C) = 0x182B; |
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104 | *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0xC) = 0x33805000; |
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105 | |||
106 | } |
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107 | |||
108 | /** Returns the mask of active interrupts. */ |
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109 | static inline uint32_t qemu_icp_irqc_get_sources(void) |
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110 | { |
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111 | return *((uint32_t *) qemu_icp_hw_map.irqc); |
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112 | } |
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113 | |||
114 | |||
115 | /** Masks interrupt. |
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116 | * |
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117 | * @param irq interrupt number |
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118 | */ |
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119 | static inline void qemu_icp_irqc_mask(uint32_t irq) |
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120 | { |
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121 | *((uint32_t *) qemu_icp_hw_map.irqc_mask) = irq; |
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122 | } |
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123 | |||
124 | |||
125 | /** Unmasks interrupt. |
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126 | * |
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127 | * @param irq interrupt number |
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128 | */ |
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129 | static inline void qemu_icp_irqc_unmask(uint32_t irq) |
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130 | { |
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3759 | pillai | 131 | *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= irq; |
3528 | pillai | 132 | } |
133 | |||
3529 | pillai | 134 | /** Initializes the icp frame buffer */ |
135 | void qemu_icp_fb_init(void) |
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136 | { |
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137 | fb_init(qemu_icp_get_fb_address(), 640, 480, 2560, VISUAL_BGR_8_8_8_0); |
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138 | } |
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3528 | pillai | 139 | |
140 | /** Initializes #qemu_icp_hw_map. */ |
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141 | void qemu_icp_hw_map_init(void) |
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142 | { |
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143 | qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE); |
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144 | qemu_icp_hw_map.kbd = hw_map(QEMU_ICP_KBD, PAGE_SIZE); |
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145 | qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE); |
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146 | qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE); |
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147 | |||
148 | qemu_icp_hw_map.rtc_freq = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_FREQ_OFFSET; |
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149 | qemu_icp_hw_map.rtc_ack = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_ACK_OFFSET; |
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150 | qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET; |
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151 | qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc + |
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152 | QEMU_ICP_IRQC_UNMASK_OFFSET; |
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153 | qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE); |
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154 | qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE); |
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155 | |||
156 | //icp_vga_init(); |
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157 | |||
158 | hw_map_init_called = true; |
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159 | } |
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160 | |||
161 | |||
162 | /** Putchar that works with qemu_icp. |
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163 | * |
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164 | * @param dev Not used. |
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165 | * @param ch Characted to be printed. |
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166 | */ |
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167 | static void qemu_icp_write(chardev_t *dev, const char ch) |
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168 | { |
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169 | *((char *) qemu_icp_hw_map.videoram) = ch; |
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170 | } |
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171 | |||
172 | /** Enables qemu_icp keyboard (interrupt unmasked). |
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173 | * |
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174 | * @param dev Not used. |
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175 | * |
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176 | * Called from getc(). |
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177 | */ |
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178 | static void qemu_icp_kbd_enable(chardev_t *dev) |
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179 | { |
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180 | qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ); |
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181 | } |
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182 | |||
183 | /** Disables qemu_icp keyboard (interrupt masked). |
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184 | * |
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185 | * @param dev not used |
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186 | * |
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187 | * Called from getc(). |
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188 | */ |
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189 | static void qemu_icp_kbd_disable(chardev_t *dev) |
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190 | { |
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191 | qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ); |
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192 | } |
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193 | |||
194 | /** Read character using polling, assume interrupts disabled. |
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195 | * |
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196 | * @param dev Not used. |
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197 | */ |
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198 | static char qemu_icp_do_read(chardev_t *dev) |
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199 | { |
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200 | char ch; |
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201 | |||
202 | while (1) { |
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203 | ch = *((volatile char *) qemu_icp_hw_map.kbd); |
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204 | if (ch) { |
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205 | if (ch == '\r') |
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206 | return '\n'; |
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207 | if (ch == 0x7f) |
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208 | return '\b'; |
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209 | return ch; |
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210 | } |
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211 | } |
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212 | } |
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213 | |||
214 | /** Process keyboard interrupt. |
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215 | * |
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216 | * @param irq IRQ information. |
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217 | * @param arg Not used. |
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218 | */ |
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219 | static void qemu_icp_irq_handler(irq_t *irq, void *arg, ...) |
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220 | { |
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221 | if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) { |
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222 | ipc_irq_send_notif(irq); |
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223 | } else { |
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224 | char ch = 0; |
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225 | |||
226 | ch = *((char *) qemu_icp_hw_map.kbd); |
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227 | if (ch == '\r') { |
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228 | ch = '\n'; |
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229 | } |
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230 | if (ch == 0x7f) { |
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231 | ch = '\b'; |
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232 | } |
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233 | chardev_push_character(&console, ch); |
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234 | } |
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235 | } |
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236 | |||
237 | static irq_ownership_t qemu_icp_claim(void) |
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238 | { |
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239 | return IRQ_ACCEPT; |
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240 | } |
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241 | |||
242 | |||
243 | /** Acquire console back for kernel. */ |
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244 | void qemu_icp_grab_console(void) |
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245 | { |
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246 | ipl_t ipl = interrupts_disable(); |
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247 | spinlock_lock(&qemu_icp_console_irq.lock); |
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248 | qemu_icp_console_irq.notif_cfg.notify = false; |
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249 | spinlock_unlock(&qemu_icp_console_irq.lock); |
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250 | interrupts_restore(ipl); |
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251 | } |
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252 | |||
253 | /** Return console to userspace. */ |
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254 | void qemu_icp_release_console(void) |
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255 | { |
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256 | ipl_t ipl = interrupts_disable(); |
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257 | spinlock_lock(&qemu_icp_console_irq.lock); |
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258 | if (qemu_icp_console_irq.notif_cfg.answerbox) { |
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259 | qemu_icp_console_irq.notif_cfg.notify = true; |
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260 | } |
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261 | spinlock_unlock(&qemu_icp_console_irq.lock); |
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262 | interrupts_restore(ipl); |
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263 | } |
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264 | |||
265 | /** Initializes console object representing qemu_icp console. |
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266 | * |
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267 | * @param devno device number. |
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268 | */ |
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269 | void qemu_icp_console_init(devno_t devno) |
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270 | { |
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271 | chardev_initialize("qemu_icp_console", &console, &qemu_icp_ops); |
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272 | stdin = &console; |
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273 | stdout = &console; |
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274 | |||
275 | irq_initialize(&qemu_icp_console_irq); |
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276 | qemu_icp_console_irq.devno = devno; |
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277 | qemu_icp_console_irq.inr = QEMU_ICP_KBD_IRQ; |
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278 | qemu_icp_console_irq.claim = qemu_icp_claim; |
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279 | qemu_icp_console_irq.handler = qemu_icp_irq_handler; |
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280 | irq_register(&qemu_icp_console_irq); |
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281 | |||
282 | qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ); |
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283 | |||
284 | sysinfo_set_item_val("kbd", NULL, true); |
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285 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
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286 | sysinfo_set_item_val("kbd.inr", NULL, QEMU_ICP_KBD_IRQ); |
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287 | sysinfo_set_item_val("kbd.address.virtual", NULL, qemu_icp_hw_map.kbd); |
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288 | } |
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289 | |||
290 | /** Starts qemu_icp Real Time Clock device, which asserts regular interrupts. |
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291 | * |
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292 | * @param frequency Interrupts frequency (0 disables RTC). |
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293 | */ |
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294 | static void qemu_icp_timer_start(uint32_t frequency) |
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295 | { |
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296 | *((uint32_t*) qemu_icp_hw_map.rtc_freq) = frequency; |
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297 | } |
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298 | |||
299 | static irq_ownership_t qemu_icp_timer_claim(void) |
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300 | { |
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301 | return IRQ_ACCEPT; |
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302 | } |
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303 | |||
304 | /** Timer interrupt handler. |
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305 | * |
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306 | * @param irq Interrupt information. |
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307 | * @param arg Not used. |
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308 | */ |
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309 | static void qemu_icp_timer_irq_handler(irq_t *irq, void *arg, ...) |
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310 | { |
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311 | /* |
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312 | * We are holding a lock which prevents preemption. |
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313 | * Release the lock, call clock() and reacquire the lock again. |
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314 | */ |
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315 | spinlock_unlock(&irq->lock); |
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316 | clock(); |
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317 | spinlock_lock(&irq->lock); |
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318 | |||
319 | /* acknowledge tick */ |
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320 | *((uint32_t*) qemu_icp_hw_map.rtc_ack) = 0; |
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321 | } |
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322 | |||
323 | /** Initializes and registers timer interrupt handler. */ |
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324 | static void qemu_icp_timer_irq_init(void) |
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325 | { |
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326 | irq_initialize(&qemu_icp_timer_irq); |
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327 | qemu_icp_timer_irq.devno = device_assign_devno(); |
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328 | qemu_icp_timer_irq.inr = QEMU_ICP_TIMER_IRQ; |
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329 | qemu_icp_timer_irq.claim = qemu_icp_timer_claim; |
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330 | qemu_icp_timer_irq.handler = qemu_icp_timer_irq_handler; |
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331 | |||
332 | irq_register(&qemu_icp_timer_irq); |
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333 | } |
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334 | |||
335 | |||
336 | /** Starts timer. |
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337 | * |
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338 | * Initiates regular timer interrupts after initializing |
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339 | * corresponding interrupt handler. |
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340 | */ |
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341 | void qemu_icp_timer_irq_start(void) |
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342 | { |
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343 | qemu_icp_timer_irq_init(); |
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344 | qemu_icp_timer_start(QEMU_ICP_TIMER_FREQ); |
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345 | } |
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346 | |||
347 | /** Returns the size of emulated memory. |
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348 | * |
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349 | * @return Size in bytes. |
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350 | */ |
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351 | size_t qemu_icp_get_memory_size(void) |
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352 | { |
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353 | //return *((int *) (QEMU_ICP_MP + QEMU_ICP_MP_MEMSIZE_OFFSET)); |
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354 | return 0x2000000; |
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355 | } |
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356 | |||
357 | /** Prints a character. |
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358 | * |
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359 | * @param ch Character to be printed. |
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360 | */ |
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361 | void qemu_icp_debug_putc(char ch) |
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362 | { |
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363 | char *addr = 0; |
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364 | if (!hw_map_init_called) { |
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365 | addr = (char *) QEMU_ICP_KBD; |
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366 | } else { |
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367 | addr = (char *) qemu_icp_hw_map.videoram; |
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368 | } |
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369 | |||
370 | if (ch == '\n') |
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371 | *(addr) = '\r'; |
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372 | *(addr) = ch; |
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373 | } |
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374 | |||
375 | /** Stops qemu_icp. */ |
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376 | void qemu_icp_cpu_halt(void) |
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377 | { |
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378 | char * addr = 0; |
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379 | if (!hw_map_init_called) { |
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380 | addr = (char *) QEMU_ICP_KBD; |
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381 | } else { |
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382 | addr = (char *) qemu_icp_hw_map.videoram; |
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383 | } |
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384 | |||
385 | *(addr + QEMU_ICP_HALT_OFFSET) = '\0'; |
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386 | } |
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387 | |||
388 | /** Gxemul specific interrupt exception handler. |
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389 | * |
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390 | * Determines sources of the interrupt from interrupt controller and |
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391 | * calls high-level handlers for them. |
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392 | * |
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393 | * @param exc_no Interrupt exception number. |
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394 | * @param istate Saved processor state. |
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395 | */ |
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396 | void qemu_icp_irq_exception(int exc_no, istate_t *istate) |
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397 | { |
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398 | uint32_t sources = qemu_icp_irqc_get_sources(); |
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399 | int i; |
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400 | |||
401 | for (i = 0; i < QEMU_ICP_IRQC_MAX_IRQ; i++) { |
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402 | if (sources & (1 << i)) { |
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403 | irq_t *irq = irq_dispatch_and_lock(i); |
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404 | if (irq) { |
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405 | /* The IRQ handler was found. */ |
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406 | irq->handler(irq, irq->arg); |
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407 | spinlock_unlock(&irq->lock); |
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408 | } else { |
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409 | /* Spurious interrupt.*/ |
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410 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", |
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411 | CPU->id, i); |
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412 | } |
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413 | } |
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414 | } |
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415 | } |
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416 | |||
417 | /** Returns address of framebuffer device. |
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418 | * |
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419 | * @return Address of framebuffer device. |
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420 | */ |
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421 | uintptr_t qemu_icp_get_fb_address(void) |
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422 | { |
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423 | if (!vga_init) { |
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424 | icp_vga_init(); |
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425 | vga_init = true; |
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426 | } |
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427 | return (uintptr_t) QEMU_ICP_FB; |
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428 | } |
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429 | |||
430 | |||
431 | /** @} |
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432 | */ |