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2128 | jermar | 1 | /* |
2238 | kebrt | 2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2128 | jermar | 3 | * All rights reserved. |
4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * |
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9 | * - Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * - Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * - The name of the author may not be used to endorse or promote products |
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15 | * derived from this software without specific prior written permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |||
29 | /** @addtogroup arm32mm |
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30 | * @{ |
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31 | */ |
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32 | /** @file |
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33 | */ |
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34 | |||
35 | #ifndef KERN_arm32_PAGE_H_ |
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36 | #define KERN_arm32_PAGE_H_ |
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37 | |||
38 | #include <arch/mm/frame.h> |
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2182 | jancik | 39 | #include <mm/mm.h> |
40 | #include <arch/exception.h> |
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2128 | jermar | 41 | |
2182 | jancik | 42 | |
2128 | jermar | 43 | #define PAGE_WIDTH FRAME_WIDTH |
44 | #define PAGE_SIZE FRAME_SIZE |
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45 | |||
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
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47 | |||
48 | #ifndef __ASM__ |
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49 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
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50 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
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51 | #else |
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52 | # define KA2PA(x) ((x) - 0x80000000) |
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53 | # define PA2KA(x) ((x) + 0x80000000) |
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54 | #endif |
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55 | |||
56 | #ifdef KERNEL |
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57 | |||
2276 | jancik | 58 | #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
59 | #define PTL1_ENTRIES_ARCH 0 |
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60 | #define PTL2_ENTRIES_ARCH 0 |
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2241 | kebrt | 61 | /* coarse page tables used (256*4 = 1KB per page) */ |
2276 | jancik | 62 | #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
2128 | jermar | 63 | |
2276 | jancik | 64 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
65 | #define PTL1_SIZE_ARCH 0 |
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66 | #define PTL2_SIZE_ARCH 0 |
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67 | #define PTL3_SIZE_ARCH ONE_FRAME |
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2242 | kebrt | 68 | |
2276 | jancik | 69 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
70 | #define PTL1_INDEX_ARCH(vaddr) 0 |
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71 | #define PTL2_INDEX_ARCH(vaddr) 0 |
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72 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
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2128 | jermar | 73 | |
2276 | jancik | 74 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
75 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
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76 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
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77 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
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2128 | jermar | 78 | |
2276 | jancik | 79 | #define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0))) |
80 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
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2147 | jancik | 81 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
82 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
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2276 | jancik | 83 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12) |
2128 | jermar | 84 | |
2276 | jancik | 85 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i)) |
86 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
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87 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
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88 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
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2128 | jermar | 89 | |
2276 | jancik | 90 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
2147 | jancik | 91 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
92 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
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2276 | jancik | 93 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
2128 | jermar | 94 | |
2276 | jancik | 95 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
96 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 ) |
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2241 | kebrt | 97 | |
98 | /* pte should point into ptl3 */ |
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2276 | jancik | 99 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
2241 | kebrt | 100 | /* pte should point into ptl3 */ |
2276 | jancik | 101 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
102 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
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2241 | kebrt | 103 | |
2128 | jermar | 104 | #ifndef __ASM__ |
105 | |||
2276 | jancik | 106 | /** Level 0 page table entry. */ |
107 | typedef struct { |
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108 | /* 01b for coarse tables, see below for details */ |
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109 | unsigned descriptor_type : 2; |
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110 | unsigned impl_specific : 3; |
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111 | unsigned domain : 4; |
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112 | unsigned should_be_zero : 1; |
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113 | /* Pointer to the coarse 2nd level page table (holding entries for small (4KB) |
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114 | * or large (64KB) pages. ARM also supports fine 2nd level page tables that |
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115 | * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison |
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116 | * with 1KB per the coarse table) |
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117 | */ |
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118 | unsigned coarse_table_addr : 22; |
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119 | } __attribute__ ((packed)) pte_level0_t; |
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120 | |||
121 | /** Level 1 page table entry (small (4KB) pages used) */ |
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122 | typedef struct { |
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123 | /* 0b10 for small pages */ |
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124 | unsigned descriptor_type : 2; |
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125 | unsigned bufferable : 1; |
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126 | unsigned cacheable : 1; |
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127 | /* access permissions for each of 4 subparts of a page |
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128 | * (for each 1KB when small pages used */ |
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129 | unsigned access_permission_0 : 2; |
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130 | unsigned access_permission_1 : 2; |
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131 | unsigned access_permission_2 : 2; |
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132 | unsigned access_permission_3 : 2; |
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133 | unsigned frame_base_addr : 20; |
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134 | } __attribute__ ((packed)) pte_level1_t; |
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135 | |||
136 | |||
137 | /* Level 1 page tables access permissions */ |
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138 | |||
139 | /** User mode: no access, privileged mode: no access */ |
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140 | #define PTE_AP_USER_NO_KERNEL_NO 0 |
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141 | /** User mode: no access, privileged mode: read/write */ |
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142 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
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143 | /** User mode: read only, privileged mode: read/write */ |
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144 | #define PTE_AP_USER_RO_KERNEL_RW 2 |
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145 | /** User mode: read/write, privileged mode: read/write */ |
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146 | #define PTE_AP_USER_RW_KERNEL_RW 3 |
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147 | |||
148 | |||
149 | /* pte_level0_t and pte_level1_t descriptor_type flags */ |
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150 | |||
151 | /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */ |
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152 | #define PTE_DESCRIPTOR_NOT_PRESENT 0 |
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153 | /** pte_level0_t coarse page table flag (used in descriptor_type) */ |
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154 | #define PTE_DESCRIPTOR_COARSE_TABLE 1 |
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155 | /** pte_level1_t small page table flag (used in descriptor type) */ |
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156 | #define PTE_DESCRIPTOR_SMALL_PAGE 2 |
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157 | |||
158 | |||
159 | /** |
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2241 | kebrt | 160 | * Sets the address of level 0 page table. |
161 | * |
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162 | * \param pt pointer to the page table to set |
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2182 | jancik | 163 | */ |
2238 | kebrt | 164 | static inline void set_ptl0_addr( pte_level0_t* pt) |
165 | { |
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2276 | jancik | 166 | asm volatile ( |
167 | "mcr p15, 0, %0, c2, c0, 0 \n" |
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168 | : |
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169 | : "r"(pt) |
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170 | ); |
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2182 | jancik | 171 | } |
2128 | jermar | 172 | |
2263 | kebrt | 173 | /** Returns level 0 page table entry flags. |
2241 | kebrt | 174 | * |
2263 | kebrt | 175 | * \param pt level 0 page table |
176 | * \param i index of the entry to return |
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2241 | kebrt | 177 | */ |
2147 | jancik | 178 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
2128 | jermar | 179 | { |
2238 | kebrt | 180 | pte_level0_t *p = &pt[i]; |
2147 | jancik | 181 | |
2256 | kebrt | 182 | return |
183 | ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) | |
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2241 | kebrt | 184 | ( 1 << PAGE_USER_SHIFT ) | |
185 | ( 1 << PAGE_READ_SHIFT ) | |
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186 | ( 1 << PAGE_WRITE_SHIFT ) | |
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187 | ( 1 << PAGE_EXEC_SHIFT ) | |
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188 | ( 1 << PAGE_CACHEABLE_SHIFT ) |
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2256 | kebrt | 189 | ; |
2238 | kebrt | 190 | } |
2147 | jancik | 191 | |
2263 | kebrt | 192 | /** Returns level 1 page table entry flags. |
2241 | kebrt | 193 | * |
2263 | kebrt | 194 | * \param pt level 1 page table |
195 | * \param i index of the entry to return |
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2241 | kebrt | 196 | */ |
2149 | jancik | 197 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
2147 | jancik | 198 | { |
2241 | kebrt | 199 | pte_level1_t *p = &pt[i]; |
2128 | jermar | 200 | |
2256 | kebrt | 201 | return |
202 | ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
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203 | ( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
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204 | ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) | |
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205 | ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
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2259 | jancik | 206 | ( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) | |
207 | ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT ) | |
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208 | ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) | |
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2147 | jancik | 209 | ( 1 << PAGE_EXEC_SHIFT ) | |
2241 | kebrt | 210 | ( p->bufferable << PAGE_CACHEABLE ) |
2256 | kebrt | 211 | ; |
2147 | jancik | 212 | } |
213 | |||
2263 | kebrt | 214 | /** Sets flags of level 0 page table entry. |
2241 | kebrt | 215 | * |
2263 | kebrt | 216 | * \param pt level 0 page table |
217 | * \param i index of the entry to be changed |
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218 | * \param flags new flags |
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2241 | kebrt | 219 | */ |
2147 | jancik | 220 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
2128 | jermar | 221 | { |
2147 | jancik | 222 | pte_level0_t *p = &pt[i]; |
2256 | kebrt | 223 | |
2241 | kebrt | 224 | if (flags & PAGE_NOT_PRESENT) { |
2256 | kebrt | 225 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
2263 | kebrt | 226 | // ensures that the entry will be recognized as valid when PTE_VALID_ARCH applied |
2259 | jancik | 227 | p->should_be_zero = 1; |
2238 | kebrt | 228 | } else { |
2256 | kebrt | 229 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
2259 | jancik | 230 | p->should_be_zero = 0; |
2147 | jancik | 231 | } |
2128 | jermar | 232 | } |
233 | |||
2263 | kebrt | 234 | /** Sets flags of level 1 page table entry. |
2241 | kebrt | 235 | * |
2263 | kebrt | 236 | * We use same access rights for the whole page. When page is not preset we |
237 | * store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct |
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238 | * page entry, see #PAGE_VALID_ARCH). |
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2241 | kebrt | 239 | * |
2263 | kebrt | 240 | * \param pt level 1 page table |
241 | * \param i index of the entry to be changed |
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242 | * \param flags new flags |
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2147 | jancik | 243 | */ |
244 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
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245 | { |
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246 | pte_level1_t *p = &pt[i]; |
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247 | |||
2241 | kebrt | 248 | if (flags & PAGE_NOT_PRESENT) { |
2256 | kebrt | 249 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
2259 | jancik | 250 | p->access_permission_3 = 1; |
2238 | kebrt | 251 | } else { |
2256 | kebrt | 252 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
2259 | jancik | 253 | p->access_permission_3 = p->access_permission_0; |
2238 | kebrt | 254 | } |
2147 | jancik | 255 | |
2238 | kebrt | 256 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
257 | |||
2241 | kebrt | 258 | /* default access permission */ |
2238 | kebrt | 259 | p->access_permission_0 = p->access_permission_1 = |
2256 | kebrt | 260 | p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; |
2238 | kebrt | 261 | |
2241 | kebrt | 262 | if (flags & PAGE_USER) { |
263 | if (flags & PAGE_READ) { |
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2238 | kebrt | 264 | p->access_permission_0 = p->access_permission_1 = |
265 | p->access_permission_2 = p->access_permission_3 = |
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2256 | kebrt | 266 | PTE_AP_USER_RO_KERNEL_RW; |
2238 | kebrt | 267 | } |
2241 | kebrt | 268 | if (flags & PAGE_WRITE) { |
2238 | kebrt | 269 | p->access_permission_0 = p->access_permission_1 = |
270 | p->access_permission_2 = p->access_permission_3 = |
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2256 | kebrt | 271 | PTE_AP_USER_RW_KERNEL_RW; |
2238 | kebrt | 272 | } |
273 | } |
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2147 | jancik | 274 | } |
275 | |||
2258 | jancik | 276 | |
2128 | jermar | 277 | extern void page_arch_init(void); |
278 | |||
2258 | jancik | 279 | extern void prefetch_abourt(int n, istate_t *istate); |
280 | extern void data_abourt(int n, istate_t *istate); |
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281 | |||
2128 | jermar | 282 | #endif /* __ASM__ */ |
283 | |||
284 | #endif /* KERNEL */ |
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285 | |||
286 | #endif |
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287 | |||
288 | /** @} |
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289 | */ |
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2147 | jancik | 290 |