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885 decky 1
/*
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 * Copyright (C) 2005 Martin Decky
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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1003 decky 29
#ifndef __ppc32_REGNAME_H__
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#define __ppc32_REGNAME_H__
885 decky 31
 
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/* Condition Register Bit Fields */
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#define	cr0	0
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#define	cr1	1
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#define	cr2	2
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#define	cr3	3
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#define	cr4	4
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#define	cr5	5
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#define	cr6	6
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#define	cr7	7
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/* General Purpose Registers (GPRs) */
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#define	r0	0
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#define	r1	1
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#define	r2	2
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#define	r3	3
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#define	r4	4
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#define	r5	5
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#define	r6	6
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#define	r7	7
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#define	r8	8
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#define	r9	9
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#define	r10	10
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#define	r11	11
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#define	r12	12
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#define	r13	13
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#define	r14	14
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#define	r15	15
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#define	r16	16
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#define	r17	17
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#define	r18	18
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#define	r19	19
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#define	r20	20
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#define	r21	21
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#define	r22	22
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#define	r23	23
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#define	r24	24
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#define	r25	25
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#define	r26	26
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#define	r27	27
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#define	r28	28
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#define	r29	29
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#define	r30	30
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#define	r31	31
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/* GPR Aliases */
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#define	sp	1
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/* Floating Point Registers (FPRs) */
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#define	fr0		0
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#define	fr1		1
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#define	fr2		2
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#define	fr3		3
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#define	fr4		4
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#define	fr5		5
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#define	fr6		6
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#define	fr7		7
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#define	fr8		8
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#define	fr9		9
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#define	fr10	10
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#define	fr11	11
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#define	fr12	12
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#define	fr13	13
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#define	fr14	14
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#define	fr15	15
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#define	fr16	16
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#define	fr17	17
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#define	fr18	18
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#define	fr19	19
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#define	fr20	20
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#define	fr21	21
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#define	fr22	22
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#define	fr23	23
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#define	fr24	24
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#define	fr25	25
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#define	fr26	26
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#define	fr27	27
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#define	fr28	28
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#define	fr29	29
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#define	fr30	30
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#define	fr31	31
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#define	vr0		0
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#define	vr1		1
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#define	vr2		2
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#define	vr3		3
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#define	vr4		4
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#define	vr5		5
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#define	vr6		6
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#define	vr7		7
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#define	vr8		8
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#define	vr9		9
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#define	vr10	10
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#define	vr11	11
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#define	vr12	12
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#define	vr13	13
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#define	vr14	14
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#define	vr15	15
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#define	vr16	16
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#define	vr17	17
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#define	vr18	18
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#define	vr19	19
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#define	vr20	20
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#define	vr21	21
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#define	vr22	22
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#define	vr23	23
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#define	vr24	24
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#define	vr25	25
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#define	vr26	26
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#define	vr27	27
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#define	vr28	28
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#define	vr29	29
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#define	vr30	30
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#define	vr31	31
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#define	evr0	0
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#define	evr1	1
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#define	evr2	2
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#define	evr3	3
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#define	evr4	4
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#define	evr5	5
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#define	evr6	6
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#define	evr7	7
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#define	evr8	8
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#define	evr9	9
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#define	evr10	10
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#define	evr11	11
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#define	evr12	12
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#define	evr13	13
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#define	evr14	14
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#define	evr15	15
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#define	evr16	16
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#define	evr17	17
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#define	evr18	18
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#define	evr19	19
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#define	evr20	20
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#define	evr21	21
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#define	evr22	22
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#define	evr23	23
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#define	evr24	24
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#define	evr25	25
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#define	evr26	26
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#define	evr27	27
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#define	evr28	28
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#define	evr29	29
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#define	evr30	30
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#define	evr31	31
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/* Special Purpose Registers (SPRs) */
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#define	xer		1
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#define lr		8
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#define ctr		9
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#define	dec		22
1058 decky 184
#define	sdr1	25
885 decky 185
#define	srr0	26
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#define srr1	27
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#define	sprg0	272
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#define	sprg1	273
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#define	sprg2	274
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#define	sprg3	275
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#define	prv		287
1068 decky 192
#define ibat0u	528
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#define ibat0l	529
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#define ibat1u	530
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#define ibat1l	531
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#define ibat2u	532
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#define ibat2l	533
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#define ibat3u	534
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#define ibat3l	535
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#define dbat0u	536
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#define dbat0l	537
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#define dbat1u	538
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#define dbat1l	539
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#define dbat2u	540
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#define dbat2l	541
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#define dbat3u	542
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#define dbat3l	543
1003 decky 208
#define hid0	1008
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1003 decky 210
/* MSR bits */
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#define msr_ir	(1 << 4)
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#define msr_dr	(1 << 5)
1478 decky 213
#define msr_ee	(1 << 15)
1003 decky 214
 
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/* HID0 bits */
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#define hid0_ice	(1 << 15)
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#define hid0_dce	(1 << 14)
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#define hid0_icfi	(1 << 11)
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#define hid0_dci	(1 << 10)
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885 decky 221
#endif