Rev 953 | Rev 964 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
913 | decky | 1 | # |
2 | # Copyright (C) 2006 Martin Decky |
||
3 | # All rights reserved. |
||
4 | # |
||
5 | # Redistribution and use in source and binary forms, with or without |
||
6 | # modification, are permitted provided that the following conditions |
||
7 | # are met: |
||
8 | # |
||
9 | # - Redistributions of source code must retain the above copyright |
||
10 | # notice, this list of conditions and the following disclaimer. |
||
11 | # - Redistributions in binary form must reproduce the above copyright |
||
12 | # notice, this list of conditions and the following disclaimer in the |
||
13 | # documentation and/or other materials provided with the distribution. |
||
14 | # - The name of the author may not be used to endorse or promote products |
||
15 | # derived from this software without specific prior written permission. |
||
16 | # |
||
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
||
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
||
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
||
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
||
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
||
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||
27 | # |
||
28 | |||
29 | #include "regname.h" |
||
30 | #include "spr.h" |
||
31 | |||
914 | decky | 32 | .data |
33 | |||
34 | flush_buffer: |
||
933 | decky | 35 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
914 | decky | 36 | |
913 | decky | 37 | .text |
38 | |||
39 | .global memsetb |
||
40 | .global memcpy |
||
956 | decky | 41 | .global flush_instruction_cache |
913 | decky | 42 | .global jump_to_kernel |
43 | |||
44 | memsetb: |
||
45 | rlwimi r5, r5, 8, 16, 23 |
||
46 | rlwimi r5, r5, 16, 0, 15 |
||
47 | |||
48 | addi r14, r3, -4 |
||
49 | |||
50 | cmplwi 0, r4, 4 |
||
51 | blt 7f |
||
52 | |||
53 | stwu r5, 4(r14) |
||
54 | beqlr |
||
55 | |||
56 | andi. r15, r14, 3 |
||
57 | add r4, r15, r4 |
||
58 | subf r14, r15, r14 |
||
59 | srwi r15, r4, 2 |
||
60 | mtctr r15 |
||
61 | |||
62 | bdz 6f |
||
63 | |||
64 | 1: |
||
65 | stwu r5, 4(r14) |
||
66 | bdnz 1b |
||
67 | |||
68 | 6: |
||
69 | |||
70 | andi. r4, r4, 3 |
||
71 | |||
72 | 7: |
||
73 | |||
74 | cmpwi 0, r4, 0 |
||
75 | beqlr |
||
76 | |||
77 | mtctr r4 |
||
78 | addi r6, r6, 3 |
||
79 | |||
80 | 8: |
||
81 | |||
82 | stbu r5, 1(r14) |
||
83 | bdnz 8b |
||
84 | |||
85 | blr |
||
86 | |||
87 | memcpy: |
||
88 | srwi. r7, r5, 3 |
||
89 | addi r6, r3, -4 |
||
90 | addi r4, r4, -4 |
||
91 | beq 2f |
||
92 | |||
93 | andi. r0, r6, 3 |
||
94 | mtctr r7 |
||
95 | bne 5f |
||
96 | |||
97 | 1: |
||
98 | |||
99 | lwz r7, 4(r4) |
||
100 | lwzu r8, 8(r4) |
||
101 | stw r7, 4(r6) |
||
102 | stwu r8, 8(r6) |
||
103 | bdnz 1b |
||
104 | |||
105 | andi. r5, r5, 7 |
||
106 | |||
107 | 2: |
||
108 | |||
109 | cmplwi 0, r5, 4 |
||
110 | blt 3f |
||
111 | |||
112 | lwzu r0, 4(r4) |
||
113 | addi r5, r5, -4 |
||
114 | stwu r0, 4(r6) |
||
115 | |||
116 | 3: |
||
117 | |||
118 | cmpwi 0, r5, 0 |
||
119 | beqlr |
||
120 | mtctr r5 |
||
121 | addi r4, r4, 3 |
||
122 | addi r6, r6, 3 |
||
123 | |||
124 | 4: |
||
125 | |||
126 | lbzu r0, 1(r4) |
||
127 | stbu r0, 1(r6) |
||
128 | bdnz 4b |
||
129 | blr |
||
130 | |||
131 | 5: |
||
132 | |||
133 | subfic r0, r0, 4 |
||
134 | mtctr r0 |
||
135 | |||
136 | 6: |
||
137 | |||
138 | lbz r7, 4(r4) |
||
139 | addi r4, r4, 1 |
||
140 | stb r7, 4(r6) |
||
141 | addi r6, r6, 1 |
||
142 | bdnz 6b |
||
143 | subf r5, r0, r5 |
||
144 | rlwinm. r7, r5, 32-3, 3, 31 |
||
145 | beq 2b |
||
146 | mtctr r7 |
||
147 | b 1b |
||
148 | |||
914 | decky | 149 | flush_instruction_cache: |
150 | |||
151 | # Flush data cache |
||
152 | |||
153 | lis r3, flush_buffer@h |
||
154 | ori r3, r3, flush_buffer@l |
||
155 | li r4, L1_CACHE_LINES |
||
156 | mtctr r4 |
||
157 | |||
158 | 0: |
||
159 | |||
160 | lwz r4, 0(r3) |
||
161 | addi r3, r3, L1_CACHE_BYTES |
||
162 | bdnz 0b |
||
163 | |||
164 | # Invalidate instruction cache |
||
165 | |||
166 | li r3, 0 |
||
167 | ori r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI) |
||
168 | mfspr r4, SPRN_HID0 |
||
169 | or r5, r4, r3 |
||
170 | isync |
||
171 | mtspr SPRN_HID0, r5 |
||
172 | sync |
||
173 | isync |
||
174 | |||
175 | # Enable instruction cache |
||
176 | |||
177 | ori r5, r4, HID0_ICE |
||
178 | mtspr SPRN_HID0, r5 |
||
179 | sync |
||
180 | isync |
||
181 | blr |
||
182 | |||
913 | decky | 183 | jump_to_kernel: |
956 | decky | 184 | mtlr r3 |
185 | blr |
||
186 |