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913 | decky | 1 | # |
2 | # Copyright (C) 2006 Martin Decky |
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3 | # All rights reserved. |
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4 | # |
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5 | # Redistribution and use in source and binary forms, with or without |
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6 | # modification, are permitted provided that the following conditions |
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7 | # are met: |
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8 | # |
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9 | # - Redistributions of source code must retain the above copyright |
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10 | # notice, this list of conditions and the following disclaimer. |
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11 | # - Redistributions in binary form must reproduce the above copyright |
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12 | # notice, this list of conditions and the following disclaimer in the |
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13 | # documentation and/or other materials provided with the distribution. |
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14 | # - The name of the author may not be used to endorse or promote products |
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15 | # derived from this software without specific prior written permission. |
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16 | # |
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17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | # |
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28 | |||
29 | #include "regname.h" |
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30 | |||
914 | decky | 31 | .data |
32 | |||
33 | flush_buffer: |
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933 | decky | 34 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
914 | decky | 35 | |
913 | decky | 36 | .text |
37 | |||
38 | .global memsetb |
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39 | .global memcpy |
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956 | decky | 40 | .global flush_instruction_cache |
913 | decky | 41 | .global jump_to_kernel |
42 | |||
43 | memsetb: |
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44 | rlwimi r5, r5, 8, 16, 23 |
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45 | rlwimi r5, r5, 16, 0, 15 |
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46 | |||
47 | addi r14, r3, -4 |
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48 | |||
49 | cmplwi 0, r4, 4 |
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50 | blt 7f |
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51 | |||
52 | stwu r5, 4(r14) |
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53 | beqlr |
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54 | |||
55 | andi. r15, r14, 3 |
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56 | add r4, r15, r4 |
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57 | subf r14, r15, r14 |
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58 | srwi r15, r4, 2 |
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59 | mtctr r15 |
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60 | |||
61 | bdz 6f |
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62 | |||
63 | 1: |
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64 | stwu r5, 4(r14) |
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65 | bdnz 1b |
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66 | |||
67 | 6: |
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68 | |||
69 | andi. r4, r4, 3 |
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70 | |||
71 | 7: |
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72 | |||
73 | cmpwi 0, r4, 0 |
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74 | beqlr |
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75 | |||
76 | mtctr r4 |
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77 | addi r6, r6, 3 |
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78 | |||
79 | 8: |
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80 | |||
81 | stbu r5, 1(r14) |
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82 | bdnz 8b |
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83 | |||
84 | blr |
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85 | |||
86 | memcpy: |
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87 | srwi. r7, r5, 3 |
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88 | addi r6, r3, -4 |
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89 | addi r4, r4, -4 |
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90 | beq 2f |
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91 | |||
92 | andi. r0, r6, 3 |
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93 | mtctr r7 |
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94 | bne 5f |
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95 | |||
96 | 1: |
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97 | |||
98 | lwz r7, 4(r4) |
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99 | lwzu r8, 8(r4) |
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100 | stw r7, 4(r6) |
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101 | stwu r8, 8(r6) |
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102 | bdnz 1b |
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103 | |||
104 | andi. r5, r5, 7 |
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105 | |||
106 | 2: |
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107 | |||
108 | cmplwi 0, r5, 4 |
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109 | blt 3f |
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110 | |||
111 | lwzu r0, 4(r4) |
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112 | addi r5, r5, -4 |
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113 | stwu r0, 4(r6) |
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114 | |||
115 | 3: |
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116 | |||
117 | cmpwi 0, r5, 0 |
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118 | beqlr |
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119 | mtctr r5 |
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120 | addi r4, r4, 3 |
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121 | addi r6, r6, 3 |
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122 | |||
123 | 4: |
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124 | |||
125 | lbzu r0, 1(r4) |
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126 | stbu r0, 1(r6) |
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127 | bdnz 4b |
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128 | blr |
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129 | |||
130 | 5: |
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131 | |||
132 | subfic r0, r0, 4 |
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133 | mtctr r0 |
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134 | |||
135 | 6: |
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136 | |||
137 | lbz r7, 4(r4) |
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138 | addi r4, r4, 1 |
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139 | stb r7, 4(r6) |
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140 | addi r6, r6, 1 |
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141 | bdnz 6b |
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142 | subf r5, r0, r5 |
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143 | rlwinm. r7, r5, 32-3, 3, 31 |
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144 | beq 2b |
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145 | mtctr r7 |
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146 | b 1b |
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147 | |||
914 | decky | 148 | flush_instruction_cache: |
149 | |||
150 | # Flush data cache |
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151 | |||
152 | lis r3, flush_buffer@h |
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153 | ori r3, r3, flush_buffer@l |
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154 | li r4, L1_CACHE_LINES |
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155 | mtctr r4 |
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156 | |||
157 | 0: |
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158 | |||
159 | lwz r4, 0(r3) |
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160 | addi r3, r3, L1_CACHE_BYTES |
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161 | bdnz 0b |
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162 | |||
163 | # Invalidate instruction cache |
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164 | |||
165 | li r3, 0 |
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1003 | decky | 166 | ori r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci) |
167 | mfspr r4, hid0 |
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914 | decky | 168 | or r5, r4, r3 |
169 | isync |
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1003 | decky | 170 | mtspr hid0, r5 |
914 | decky | 171 | sync |
172 | isync |
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173 | |||
174 | # Enable instruction cache |
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175 | |||
1003 | decky | 176 | ori r5, r4, hid0_ice |
177 | mtspr hid0, r5 |
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914 | decky | 178 | sync |
179 | isync |
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180 | blr |
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181 | |||
913 | decky | 182 | jump_to_kernel: |
1022 | decky | 183 | |
184 | # r3 = kernel_start (va) |
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185 | # r4 = memmap (pa) |
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186 | # r5 = real_mode (pa) |
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187 | |||
188 | mtspr srr0, r5 |
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189 | |||
190 | # jumps to real_mode |
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191 | |||
192 | mfmsr r5 |
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193 | lis r6, ~0@h |
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194 | ori r6, r6, ~(msr_ir | msr_dr)@l |
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195 | and r5, r5, r6 |
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196 | mtspr srr1, r5 |
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197 | rfi |
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198 | |||
199 | .section REALMODE |
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200 | .align 12 |
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201 | .global real_mode |
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202 | |||
203 | real_mode: |
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204 | |||
205 | # fill segment registers |
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206 | |||
207 | li r5, 16 |
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208 | mtctr r5 |
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209 | li r5, 0 |
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210 | li r6, 0 |
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211 | |||
212 | seg_fill: |
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213 | |||
214 | mtsrin r6, r5 |
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215 | addis r5, r5, 0x1000 # move to next SR |
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216 | addis r6, r6, 0x10 # add 256 MB, move to next SR |
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217 | |||
218 | bdnz seg_fill |
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219 | |||
220 | # bootstrap kernel |
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221 | # |
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222 | # r3 = kernel_start (va) |
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223 | # r4 = memmap (pa) -> r10 |
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224 | |||
225 | mtspr srr0, r3 |
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226 | |||
227 | mfmsr r5 |
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228 | ori r5, r5, (msr_ir | msr_dr)@l |
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229 | mtspr srr1, r5 |
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230 | |||
964 | decky | 231 | mr r10, r4 |
1022 | decky | 232 | rfi |