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1 jermar 1 
/*
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include <arch/pm.h>
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#include <config.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <arch/interrupt.h>
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#include <arch/asm.h>
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#include <arch/context.h>
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#include <panic.h>
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/*
11 jermar 39 
 * Early ia32 configuration functions and data structures.
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 */
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/*
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 * We have no use for segmentation so we set up flat mode. In this
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 * mode, we use, for each privilege level, two segments spanning the
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 * whole memory. One is for code and one is for data.
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 */
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struct descriptor gdt[GDT_ITEMS] = {
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    /* NULL descriptor */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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    /* KTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* KDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
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    /* UTEXT descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* UDATA descriptor */
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    { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
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    /* TSS descriptor - set up will be completed later */
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    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
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};
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static struct idescriptor idt[IDT_ITEMS];
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static struct tss tss;
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struct tss *tss_p = NULL;
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/* gdtr is changed by kmp before next CPU is initialized */
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struct ptr_16_32 gdtr __attribute__ ((section ("K_DATA_START"))) = { .limit = sizeof(gdt), .base = (__address) gdt };
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struct ptr_16_32 idtr __attribute__ ((section ("K_DATA_START")))= { .limit = sizeof(idt), .base = (__address) idt };
1 jermar 71 
 
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void gdt_setbase(struct descriptor *d, __address base)
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{
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        d->base_0_15 = base & 0xffff;
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        d->base_16_23 = (base >> 16) & 0xff;
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        d->base_24_31 = (base >> 24) & 0xff;
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}
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void gdt_setlimit(struct descriptor *d, __address limit)
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{
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        d->limit_0_15 = limit & 0xffff;
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        d->limit_16_19 = (limit >> 16) & 0xf;
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}
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void idt_setoffset(struct idescriptor *d, __address offset)
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{
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	d->offset_0_15 = offset & 0xffff;
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	d->offset_16_31 = offset >> 16;
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}
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void tss_initialize(struct tss *t)
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{
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	memsetb((__address) t, sizeof(struct tss), 0);
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}
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/*
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 * This function takes care of proper setup of IDT and IDTR.
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 */
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void idt_init(void)
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{
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	struct idescriptor *d;
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	int i;
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	for (i = 0; i < IDT_ITEMS; i++) {
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		d = &idt[i];
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		d->unused = 0;
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		d->selector = selector(KTEXT_DES);
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		d->access = AR_PRESENT | AR_INTERRUPT;	/* masking interrupt */
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		if (i == VECTOR_SYSCALL) {
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			/*
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			 * The syscall interrupt gate must be calleable from userland.
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			 */
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			d->access |= DPL_USER;
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		}
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		idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
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		trap_register(i, null_interrupt);
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	}
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	trap_register(13, gp_fault);
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}
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void pm_init(void)
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{
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	struct descriptor *gdt_p = (struct descriptor *) gdtr.base;
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	/*
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	 * Each CPU has its private GDT and TSS.
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	 * All CPUs share one IDT.
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	 */
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	if (config.cpu_active == 1) {
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		idt_init();
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		/*
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		 * NOTE: bootstrap CPU has statically allocated TSS, because
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		 * the heap hasn't been initialized so far.
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		 */
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		tss_p = &tss;
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	}
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	else {
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		tss_p = (struct tss *) malloc(sizeof(struct tss));
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		if (!tss_p)
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			panic(PANIC "could not allocate TSS\n");
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	}
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	tss_initialize(tss_p);
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	gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
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	gdt_p[TSS_DES].special = 1;
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	gdt_p[TSS_DES].granularity = 1;
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	gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
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	gdt_setlimit(&gdt_p[TSS_DES], sizeof(struct tss) - 1);
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	/*
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	 * As of this moment, the current CPU has its own GDT pointing
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	 * to its own TSS. We just need to load the TR register.
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	 */
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	__asm__("ltr %0" : : "r" ((__u16) selector(TSS_DES)));
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}